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Architecture
17.2.1.3 Compare Mode Functionality
When Compare Enable TCLR (CE bit) is set to 1, the timer value (TCRR) is permanently compared to
the value held in timer match register (TMAR). TMAR value can be loaded at any time (timer counting
or stop). When the TCRR and the TMAR values match, an interrupt can be issued if the
IRQENABLE_SET (MAT_EN_FLAG bit) is set. The right programming way is to write a compare value
in TMAR register before setting TCLR (CE bit) to avoid any unwanted interrupt due to a reset value
matching effect.
The dedicated output pin (PORTIMERPWM) can be programmed through TCLR (TRG and PT bits) to
generate one positive pulse (TIMER clock duration) or to invert the current value (toggle mode) when
an overflow and a match occur.
17.2.1.4 Prescaler Functionality
A prescaler counter can be used to divide the timer counter input clock frequency. The prescaler is
enabled when TCLR bit 5 is set (PRE). The 2n division ratio value (PTV) can be configured in the
TCLR register. The prescaler counter is reset when the timer counter is stopped or reloaded on the fly.
Contexts
Overflow (when Auto-reload on)
TCRR Write
TTGR Write
Stop
17.2.1.5 Pulse-Width Modulation
The timer can be configured to provide a programmable pulse-width modulation (PORTIMERPWM)
output. The PORTIMERPWM output pin can be configured to toggle on specified event. TCLR (TRG
bits) determines on which register value the PORTIMERPWM pin toggles. Either overflow or match can
be used to toggle the PORTIMERPWM pin, when a compare condition occurs.
In case of overflow and match mode, the match event will be ignored from the moment the mode was
set-up until the first overflow event occurs (see
The TCLR (SCPWM bit) can be programmed to set or clear the PORTIMERPWM output signal while
the counter is stopped or the triggering is off only. This allows fixing a deterministic state of the output
pin when modulation is stopped. The modulation is synchronously stopped when TRG bit is cleared and
overflow occurred.
In the following timing diagram, the internal overflow pulse is set each time (FFFF FFFFFh – TLDR + 1)
value is reached, and the internal match pulse is set when the counter reaches TMAR register value.
According to TCLR (TRG and PT bits) programming value, the timer provides pulse or PWM on the
output pin (PORTIMERPWM).
The TLDR and TMAR registers must keep values smaller than the overflow value (FFFF FFFFh) with at
least 2 units. In case the PWM trigger events are both overflow and match, the difference between the
values kept in TMAR register and the value in TLDR must be at least 2 units. When match event is
used the compare mode TCLR (CE) must be set.
In
Figure
17-5, TCLR (SCPWM bit) is cleared to 0. In
1638
Timers
Preliminary
Table 17-2. Prescaler Functionality
Prescaler Counter
Reset
Reset
Reset
Reset
Figure
17-4).
Figure
© 2011, Texas Instruments Incorporated
Timer Counter
TLDR
TCRR
TLDR
Frozen
17-6, TCLR (SCPWM bit) is set to 1.
SPRUGX9 – 15 April 2011
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