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Architecture
3. The memory base/limit registers should not be configured such that the address of the transaction
lies in the range specified by the memory base/limit registers. Otherwise, the transaction will be
discarded as a misrouted packet.
4. It is not possible to use configuration type transactions in this mode as RC cannot be a target of
configuration transactions. Such transactions will be invalid and loopback will not work.
13.2.7 L3 Memory Map
The system memory mapping of the device is broken into three levels (Level 1, 2, and 3) of granularity
for target address spaces allocation for easier address decoding capability. The Address Spaces
required for PCIe Usage lies within Level 3 (L3) Memory/Region. See the Chip Level chapter or the
data manual for more information.
Some processors within the device may re-map these targets to different PCIe addresses through an
internal or external MMU. Processors without MMUs and other bus masters will use these OCP/Internal
addresses to access L3 regions. Note that not all masters have access to all L3 regions but only those
with defined connectivity. See the data manual or the Chip Level chapter for more information.
The OCP/Internal address block accessed by PCIESS is 256MB wide (within L3 region) with starting
address of 2000 0000h and ending address of 2FFF FFFFh. This is also referred to Address Space
One within PCIe.
Another OCP/Internal address block accessed by PCIESS is a16MB wide block (within L3 region) with
starting address of 5100_0000h and ending address of 51FF FFFFh. This address region is referred to
Address Space Zero within PCIe.
Two more additional registers within the Control Module (also within L3 region) PCIE_CFG and
PCIE_TEST_CTRL are used by the PCIe to configure the PHY PLL, PCIe Mode of operation, Test
Mode Patterns, etc.
Four more additional registers within the Power Reset and Control Module (also within L3 region) are
used to control the PCIe controller reset status and release states as well as clock enable/disable
capabilities. The PM_DEFAULT_PWRSTST and RM_DEFAULT_RSTCTRL registers are used to
control reset related tasks while CM_DEFAULT_PCI_CLKSTCTRL and CM_DEFAULT_PCI_CLKCTRL
are used to control clocking related functions.
13.2.8 Reset Considerations
The PCIESS supports the Conventional Reset mechanism that is specified within the PCI Express
Specification. Both hardware and software reset are supported.
No support for the Functional Level reset is needed since the PCIESS supports a single function.
13.2.8.1 Software Reset Considerations
Software reset is issued via the transmission of TS1 Ordered Sets.
13.2.8.2 Hardware Reset Considerations
Hardware reset is caused while power is being sourced to the device. The SoC level Power On Reset
acts as the power on reset for PCIESS.
13.2.8.3 PCIe Boot Capability
The device supports PCIe boot capability as an Endpoint. No support for RC bootmode. See Bootmode
configuration details for the applicable settings of the Bootmode pins.
1286
Peripheral Component Interconnect Express (PCIe)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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