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If the host CPU writes to the Write FIFO, independent of a transmit DMA request, the WFIFO will
accept host writes until full. After this point, excess data will be discarded.
Note that when the WFIFO is first enabled, it will immediately issue a transmit DMA request to the host.
This is because it begins in an empty state, and is therefore ready to accept data.
10.2.8.2.1.1 Transmit DMA Event Pacer
The AFIFO may be configured to delay making a transmit DMA request to the host until the Write FIFO
has enough space for a specified number of words. In this situation, the number of transmit DMA
requests to the host or DMA controller is reduced.
If the Write FIFO has space to accept WNUMEVT 32-bit words, it generates a transmit DMA request to
the host and then waits for a response. Once WNUMEVT words have been written to the FIFO, it
checks again to see if there is space for WNUMEVT 32-bit words. If there is space, it generates another
transmit DMA request to the host, and so on. In this fashion, the Write FIFO will attempt to stay filled.
Note that if transmit DMA event pacing is desired, WFIFOCTL.WNUMEVT should be set to a non-zero
integer multiple of the value in WFIFOCTL.WNUMDMA. If transmit DMA event pacing is not desired,
then the value in WFIFOCTL.WNUMEVT should be set equal to the value in WFIFOCTL.WNUMDMA.
10.2.8.2.2 AFIFO Data Reception
When the Read FIFO is disabled, receive DMA requests pass through directly from McASP to the
host/DMA controller. Whether the RFIFO is enabled or disabled, the McASP generates receive DMA
requests as needed; the AFIFO is "invisible" to the McASP.
When the Read FIFO is enabled, receive DMA requests from the McASP are sent to the AFIFO, which
in turn generates receive DMA requests to the host/DMA controller.
If the Read FIFO is enabled and the McASP makes a receive DMA request, the RFIFO reads
RNUMDMA 32-bit words from the McASP, if and when the RFIFO has space for RNUMDMA words. If it
does not, the RFIFO waits until this condition has been satisfied; at that point, it reads RNUMDMA
words from the McASP. (See description for RFIFOCTL.RNUMDMA in
If the host CPU reads the Read FIFO, independent of a receive DMA request, and the RFIFO at that
time contains less than RNUMEVT words, those words will be read correctly, emptying the FIFO.
10.2.8.2.2.1 Receive DMA Event Pacer
The AFIFO may be configured to delay making a receive DMA request to the host until the Read FIFO
contains a specified number of words. In this situation, the number of receive DMA requests to the host
or DMA controller is reduced.
If the Read FIFO contains at least RNUMEVT 32-bit words, it generates a receive DMA request to the
host and then waits for a response. Once RNUMEVT 32-bit words have been read from the RFIFO, the
RFIFO checks again to see if it contains at least another RNUMEVT words. If it does, it generates
another receive DMA request to the host, and so on. In this fashion, the Read FIFO will attempt to stay
empty.
Note that if receive DMA event pacing is desired, RFIFOCTL.RNUMEVT should be set to a non-zero
integer multiple of the value in RFIFOCTL.RNUMDMA. If receive DMA event pacing is not desired, then
the value in RFIFOCTL.RNUMEVT should be set equal to the value in RFIFOCTL.RNUMDMA.
10.2.8.2.3 Arbitration Between Transmit and Receive DMA Requests
If both the WFIFO and the RFIFO are enabled and a transmit DMA request and receive DMA request
occur simultaneously, priority is given to the transmit DMA request. Once a transfer is in progress, it is
allowed to complete.
If only the WFIFO is enabled and a transmit DMA request and receive DMA request occur
simultaneously, priority is given to the transmit DMA request. Once a transfer is in progress, it is
allowed to complete.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Section
10.3.45.)
Multichannel Audio Serial Port (McASP)
Architecture
1045
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