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20.4 Communications Port Programming Interface (CPPI) 4.1 DMA
The CPPI DMA module supports the transmission and reception of USB packets. The CPPI DMA is
designed to facilitate the segmentation and reassembly of CPPI compliant packets to/from smaller data
blocks that are natively compatible with the specific requirements of each networking port. Multiple Tx
and Rx channels are provided for all endpoints (excluding endpoint 0) within the DMA allowing multiple
segmentation or reassembly operations to be effectively performed in parallel (but not actually
simultaneously). The DMA controller maintains state information for each of the ports/channels which
allows packet segmentation and reassembly operations to be time division multiplexed between
channels in order to share the underlying DMA hardware. A DMA scheduler is used to control the
ordering and rate at which this multiplexing occurs.
The CPPI (version 4.1) DMA controller sub-module is a common 15 port DMA controller. It supports 15
Tx and 15 Rx channels and each port attaches to the associated endpoint in the controller. Port 1 maps
to endpoint 1 and Port 2 maps to endpoint 2 and so on with Port 15 mapped to endpoint 15; endpoint 0
can not utilize the DMA and the firmware is responsible to load or offload the endpoint 0 FIFO via CPU.
20.4.1 CPPI Terminology
Host — The host is an intelligent system resource that configures and manages each communications
control module. The host is responsible for allocating memory, initializing all data structures, and
responding to port interrupts.
Main Memory — The area of data storage managed by the CPU. The CPPI DMA (CDMA) reads and
writes CPPI packets from and to main memory. This memory can exist internal or external from the
device.
Queue Manager (QM) — The QM is responsible for accelerating management of a variety of Packet
Queues and Free Descriptor / Buffer Queues. It provides status indications to the CDMA Scheduler
when queues are empty or full.
CPPI DMA (CDMA) — The CDMA is responsible for transferring data between the CPPI FIFO and
Main Memory. It acquires free Buffer Descriptor from the QM (Receive Submit Queue) for storage of
received data, posts received packets pointers to the Receive Completion Queue, transmits packets
stored on the Transmit Submit Queue (Transmit Queue) , and posts completed transmit packets to the
Transmit Completion Queue.
CDMA Scheduler (CDMAS) — The CDMAS is responsible for scheduling CDMA transmit and receive
operations. It uses Queue Indicators from the QM and the CDMA to determine the types of operations
to schedule.
CPPI FIFO — The CPPI FIFO provides FIFO interfaces (for each of the 15 transmit and 15 receive
endpoints).
Transfer DMA (XDMA) — The XDMA receives DMA requests from the Mentor USB 2.0 Core and
initiates DMAs to the CPPI FIFO.
Endpoint FIFOs — The Endpoint FIFOs are the USB packet storage elements used by the Mentor
USB 2.0 Core for packet transmission or reception. The XDMA transfers data between the CPPI FIFO
and the Endpoint FIFOs for transmit operations and between the Endpoint FIFOs and the CPPI FIFO
for receive operations.
Port — A port is the communications module (peripheral hardware) that contains the control logic for
Direct Memory Access for a single transmit/receive interface or set of interfaces. Each port may have
multiple communication channels that transfer data using homogenous or heterogeneous protocols. A
port is usually subdivided into transmit and receive pairs which are independent of each other. Each
endpoint, excluding endpoint 0, has its own dedicated port.
Channel — A channel refers to the sub-division of information (flows) that is transported across ports.
Each channel has associated state information. Channels are used to segregate information flows
based on the protocol used, scheduling requirements (example: CBR, VBR, ABR), or concurrency
requirements (that is, blocking avoidance). All fifteen ports per USB Module have dedicated single
channels, channel 0, associated for their use in a USB application.
SPRUGX9 – 15 April 2011
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Preliminary
Communications Port Programming Interface (CPPI) 4.1 DMA
© 2011, Texas Instruments Incorporated
1795
Universal Serial Bus (USB)
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