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It is possible that the generation of interrupts has been reduced to an unacceptable delay due a lack of
differed bits or thresholds set to too large of a number. A watch dog timer has been added to the design
which provides a secondary method of generating the interrupts. This system uses the USB start of
frame pulse from the Mentor core, a counter, a threshold, and an enable. This logic is similar as
compared with the differed bit logic. The frame sync pulse frequency is 1kHz in full-speed or low-speed
mode, or 8kHz is high-speed mode.
Example 1: The DMA threshold is set to 10 and the frame threshold is set to 3 for a specific endpoint.
Let's assume that the expected packet completion frequency is 5 completed packets per frame. In this
example the first frame had 5 packets completed. The second frame had 5 packets completed. An
interrupt is generated after the 2nd frame.
Example 2: The DMA threshold is set to 10 and the frame threshold is set to 3 for a specific endpoint.
Let's assume that the expected packet completion frequency is 5 completed packets per frame. In this
example the first frame had 5 packets completed. The second frame had only 2 packets completed and
the third frame had 0 packets completed. There was some error or delay that caused the remaining
packets to not complete. An interrupt is generated after the 3rd frame.
In both examples software will not be able to determine whether the interrupt was generated due to
DMA threshold or frame threshold.
Each of the 60 Packet completions will have a frame counter, frame threshold, and frame enable. If the
frame counter exceeds the frame threshold; then an interrupt will be generated. This assumes the
frame enable counter has been enabled.
The registers for the 60 frame thresholds are stored in: USBSS_IRQ_FRAME_THRESHOLD_ab_c.
Where:
(a) Tx or Rx
(b) 0 or 1
(c) 0, 1, 2, or 3
The 60 frame enables are stored in registers: USBSS IRQ_FRAME_ENABLE_0 and USBSS
IRQ_FRAME_ENABLE_1.
The individual frame count registers will be reset to zero when one of the below conditions occurs:
•
Reset signal is active.
•
Packet completion threshold has been exceeded.
•
Packet completion count is equal to 255.
•
Frame count threshold has been exceeded.
•
Frame count is equal to 255.
When the low to high transition occurs for any of the four CPPI DMA Packet completions, a hardware
signal is sent to the MODIRQ module. This will cause an interrupt (if enabled via software). When all
packets have been removed from the queue, the pending signal is returned to a 0. Software may
choose to use one of the unassigned queues if an interrupt is not wanted upon the completion of a
packet.
The starvation interrupts occur when the queue manager cannot allocate a buffer for an Rx buffer. This
can occur either at the start of a packet or in the middle of a series of packets.
The interrupts listed in
IRQENABLE_SET (or IRQENABLE_CLR) bits in the MMR registers.
To clear the interrupts it is required to write 1's to the IRQSTAUS registers. It is possible to manually
set the interrupts by writing 1's to the IRQSTATUS_RAW registers.
SPRUGX9 – 15 April 2011
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Preliminary
Table 20-27
can be enabled (or disabled) by setting (or clearing) the appropriate
© 2011, Texas Instruments Incorporated
Interrupt Support
1823
Universal Serial Bus (USB)
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