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Registers
11.3.3 McBSP Serial Port Control Register 2 (SPCR2_REG)
The McBSP_SPCR2_REG register is shown in
31
15
7
6
FRST
GRST
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-10
Reserved
9
FREE
8
SOFT
7
FRST
6
GRST
5-4
XINTM
3
XSYNCERR
2
XEMPTY
1
XRDY
1178
Multichannel Buffered Serial Port (McBSP)
Preliminary
Figure 11-35. McBSP_SPCR2_REG
Reserved
R-0
5
4
XINTM
R/W-0
Table 11-22. McBSP_SPCR2_REG Field Descriptions
Value
Description
0
Reserved
Free Running Mode
(When this bit is set, the module ignores the Msuspend input)
0
Free running mode is disabled
1
Free running mode is enabled
Soft bit.
0
SOFT Mode is disabled: the McBSP module stops its activity immediately following MSuspend
assertion.
1
SOFT Mode is enabled: the McBSP module freezes its state after completion of the current
operation when MSuspend is asserted.
Frame-Sync Generator Reset.
0
Frame-synchronization logic is reset. Frame-sync signal FSG is not generated by the sample-rate
generator.
1
Frame-sync signal FSG is generated after (FPER+1) number of CLKG clocks; i.e., all frame
counters are loaded with their programmed values.
Sample-Rate Generator Reset.
0
SRG is reset.
1
SRG is pulled out of reset. CLKG is driven as per programmed value in SRG registers (SRGR[1,2])
Transmit Interrupt Mode (legacy).
0
Transmit interrupt is driven by XRDY.
1h
Transmit interrupt generated by end-of-frame.
2h
Transmit interrupt generated by a new frame synchronization.
3h
Transmit interrupt generated by XSYNCERR.
Transmit Synchronization Error.
(Writing 0 to this bit clear the legacy transmit interrupt if asserted due to XSYNCERROR condition).
0
No synchronization error.
1
Synchronization error detected by McBSP.
Transmit Shift Register XSR Empty.
0
XSR is empty.
1
XSR is not empty.
Transmitter ready.
0
Transmitter is not ready.
1
Transmitter is ready for new data in DXR.
© 2011, Texas Instruments Incorporated
Figure 11-35
and described in
Reserved
R-0
10
3
2
XSYNCERR
XEMPTY
R/W-0
R-0
www.ti.com
Table
11-22.
16
9
8
FREE
SOFT
R/W-0
R/W-0
1
0
XRDY
XRST
R-0
R/W-0
SPRUGX9 – 15 April 2011
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