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20.3.1.1 Control Transactions:Peripheral Mode
Endpoint 0 is the main control endpoint of the core. The software is required to handle all the standard
device requests that may be sent or received via endpoint 0. These are described in Universal Serial
Bus Specification, Revision 2.0, Chapter 9. The protocol for these device requests involves different
numbers and types of transactions per request/command. To accommodate this, the software needs to
take a state machine approach to command decoding and handling.
The Standard Device Requests received by a USB peripheral device can be divided into three
categories: Zero Data Requests (in which all the information is included in the command; no additional
data is required), Write Requests (in which the command will be followed by additional data), and Read
Requests (in which the device is required to send data back to the host).
This section looks at the sequence of actions that the software must perform to process these different
types of device request.
NOTE: The Setup packet associated with any standard device request should include an 8-byte
command. Any setup packet containing a command field other than 8 bytes will be automatically
rejected by the controller.
20.3.1.1.1 Zero Data Requests: Peripheral Mode
Zero data requests have all their information included in the 8-byte command and require no additional
data to be transferred. Examples of Zero Data standard device requests are:
•
SET_FEATURE
•
CLEAR_FEATURE
•
SET_ADDRESS
•
SET_CONFIGURATION
•
SET_INTERFACE
The sequence of events will begin, as with all requests, when the software receives an endpoint 0
interrupt. The RXPKTRDY bit of PERI_CSR0 (bit 0) will also have been set. The 8-byte command
should then be read from the endpoint 0 FIFO, decoded and the appropriate action taken.
For example, if the command is SET_ADDRESS, the 7-bit address value contained in the command
should be written to the FADDR register at the completion of the command. The PERI_CSR0 register
should be written by setting the SERV_RXPKTRDY bit (bit 6) (indicating that the command has been
read from the FIFO) and also setting the DATAEND bit (bit 3) (indicating that no further data is
expected for this request). The interval between setting SERV_RXPKTRDY bit and DATAEND bit
should be very small to avoid getting a SETUPEND error condition. It is highly recommended to set
both bits at the same time.
When the host moves to the status stage of the request, a second endpoint 0 interrupt will be
generated to indicate that the request has completed. No further action is required from the software.
The second interrupt is just a confirmation that the request completed successfully. For
SET_ADDRESS command, the address should be written to FADDR register at the completion of the
command, i.e. when the status stage interrupt is received.
If the command is an unrecognized command, or for some other reason cannot be executed, then
when it has been decoded, the PERI_CSR0 register should be written to set the SERV_RXPKTRDY bit
(bit 6) and to set the SENDSTALL bit (bit 5). When the host moves to the status stage of the request,
the controller will send a STALL packet telling the host that the request was not executed. A second
endpoint 0 interrupt will be generated and the SENTSTALL bit (bit 2 of PERI_CSR0) will be set.
If the host sends more data after the DATAEND bit has been set, then the controller will send a STALL
packet automatically. An endpoint 0 interrupt will be generated and the SENTSTALL bit (bit 2 of
PERI_CSR0) will be set.
NOTE: DMA is not supported for endpoint 0; endpoint 0 is always serviced via CPU.
20.3.1.1.2 Write Requests: Peripheral Mode
Write requests involve an additional packet (or packets) of data being sent from the host after the
8-byte command. An example of a Write standard device request is: SET_DESCRIPTOR.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Protocol Description(s)
1761
Universal Serial Bus (USB)
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