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When the endpoint is first configured, the endpoint data toggle should be cleared to 0 either by using
the DATATOGWREN and DATATOG bits of HOST_RXCSR (bit 10 and bit 9) to toggle the current
setting or by setting the CLRDATATOG bit of HOST_RXCSR (bit 7). This will ensure that the data
toggle (which is handled automatically by the controller) starts in the correct state. Also if there are any
data packets in the FIFO (indicated by the RXPKTRDY bit (bit 0 of HOST_RXCSR) being set), they
should be flushed by setting the FLUSHFIFO bit of HOST_RXCSR (bit 4).
NOTE: It may be necessary to set this bit twice in succession if double buffering is enabled.
20.3.2.2.1.2 Bulk IN Operation: Host Mode
When Bulk data is required from the USB peripheral device, the software should set the REQPKT bit in
the corresponding HOST_RXCSR register (bit 5). The controller will then send an IN token to the
selected peripheral endpoint and waits for data to be returned.
If data is correctly received, RXPKTRDY bit of HOST_RXCSR (bit 0) is set. If the USB peripheral
device responds with a STALL, RXSTALL bit (bit 6 of HOST_RXCSR) is set. If a NAK is received, the
controller tries again and continues to try until either the transaction is successful or the
POLINTVL_NAKLIMIT set in the HOST_RXINTERVAL register is reached. If no response at all is
received, two further attempts are made before the controller reports an error by setting the ERROR bit
of HOST_RXCSR (bit 2).
The controller then generates the appropriate endpoint interrupt, whereupon the software should read
the corresponding HOST_RXCSR register to determine whether the RXPKTRDY, RXSTALL, ERROR
or DATAERR_NAKTIMEOUT bit is set and act accordingly. If the DATAERR_NAKTIMEOUT bit is set,
the controller can be directed either to continue trying this transaction (until it times out again) by
clearing the DATAERR_NAKTIMEOUT bit or to abort the transaction by clearing REQPKT bit before
clearing the DATAERR_NAKTIMEOUT bit.
The packets received should not exceed the size specified in the RXMAXP register (as this should be
the value set in the wMaxPacketSize field of the endpoint descriptor sent to the host).
In the general case, the application software (if CPU is servicing the endpoint) will need to read each
packet from the FIFO individually. If large blocks of data are being transferred, the overhead of calling
an interrupt service routine to unload each packet can be avoided by using DMA.
Note: When using DMA, see CPPI DMA section for the proper configuration of the core register,
HOST_RXCSR.
20.3.2.2.1.3 Bulk IN Error Handling: Host Mode
If the target wants to shut down the Bulk IN pipe, it will send a STALL response to the IN token. This
will result in the RXSTALL bit of HOST_RXCSR (bit 6) being set.
20.3.2.2.2 Bulk OUT Transactions: Host Mode
A Bulk OUT transaction may be used to transfer non-periodic data from the host to the USB peripheral.
Following optional features are available for use with a Tx endpoint used in Host mode to transmit this
data:
•
Double packet buffering: When enabled, up to two packets can be stored in the FIFO awaiting
transmission to the peripheral device. Double packet buffering is enabled by setting the DPB bit of
TXFIFOSZ register (bit 4).
•
DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint
is able to accept another packet in its FIFO. This feature can be used to allow the DMA controller to
load packets into the FIFO without processor intervention. For more information on using DMA,
consult the section discussing CPPI DMA.
When DMA is enabled and DMAMODE bit in HOST_TXCSR register is set, an endpoint interrupt
will not be generated for completion of packet reception. An endpoint interrupt will be generated only
in the error conditions.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Protocol Description(s)
1789
Universal Serial Bus (USB)
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