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typedef struct {
PioSetupDW0 DW0;
PioSetupDW1 DW1;
PioSetupDW2 DW2;
PioSetupDW3 DW3;
PioSetupDW4 DW4;
}PIOSetupFis;
//-----------PIO Setup FIS end D2H Reg FIS-------
typedef struct {
Uint32 B0FisType:8;//bits[7:0]
Uint32 BYTE1:8;
Uint32 B2Status:8;
Uint32 B3Errror:8;//bits[31:24]
}D2HRegDW0;
typedef struct {
Uint32 B0LbaLow:8; //bits[7:0]
Uint32 B1LbaMid:8; //bits[15:8]
Uint32 B2LbaHigh:8;//bits[23:16]
Uint32 B3Device:8; //bits[31:24]
}D2HRegDW1;
typedef struct {
Uint32 B0LbaLowExp:8; //bits[7:0]
Uint32 B1LbaMidExp:8; //bits[15:8]
Uint32 B2LbaHighExp:8;//bits[23:16]
Uint32 B3Rsv:8;
}D2HRegDW2;
typedef struct {
Uint32 B0SecCnt:8;
Uint32 B1SecCntExp:8; //bits[15:8]
Uint32 HW1Rsv:16;
}D2HRegDW3;
typedef struct {
Uint32 W0Rsv;
}D2HRegDW4;
typedef struct {
D2HRegDW0 DW0;
D2HRegDW1 DW1;
D2HRegDW2 DW2;
D2HRegDW3 DW3;
D2HRegDW4 DW4;
}D2HRegFis;
//-----------D2H Reg FIS end Set Device Bits FIS-
// The Set Device Bit FIS definition does not contain the 2nd Word required
//
for Native Command Queueing. This second word is the SACTVE register and
//
the AHCI takes care of updating P0SACT register at its location.
typedef struct {
Uint32 B0FisType:8;//bits[7:0]
Uint32 BYTE1:8;
Uint32 B2Status:8; //bits[23:16]
Uint32 B3Errror:8; //bits[31:24]
}SetDevBitsDW0;
typedef struct {
Uint32 W1Rsv;
}SetDevBitsDW1;
typedef struct {
SetDevBitsDW0 DW0;
SetDevBitsDW1 DW1;
}SetDevBitsFis;
SPRUGX9 – 15 April 2011
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Preliminary
//bits[15:8]
//bits[23:16]
//bits[31:24]
//bits[7:0]
//bits[31:16]
//bits[31:0]
//bits[15:8]
//bits[31:0]
© 2011, Texas Instruments Incorporated
Use Cases
Serial ATA (SATA) Controller
1579
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