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Registers
Table 9-30. Control Register (SD_HCTL) Field Descriptions (continued)
Bit
Field
18
RWC
17
CR
16
SBGR
15-12
Reserved
11-9
SDVS
8
SDBP
7
CDSS
6
CDTL
5
Reserved
4-3
986
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Preliminary
Value
Description
Read wait control. The read wait function is optional only for SDIO cards. If the card supports read
wait, this bit must be enabled, then requesting a stop at block gap (SD_HCTL[16] SBGR bit)
generates a read wait period after the current end of block. Be careful, if read wait is not supported
it may cause a conflict on SD_DAT line.
0
Disable read wait control. Suspend/resume cannot be supported.
1
Enable read wait control
Continue request. This bit is used to restart a transaction that was stopped by requesting a stop at
block gap (SD_HCTL[16] SBGR bit). Set this bit to 1 restarts the transfer. The bit is automatically
cleared to 0 by the host controller when transfer has restarted, that is, SD_DAT line is active
(SD_PSTATE[2] DLA bit) or transferring data (SD_PSTATE[8] WTA bit).
The Stop at block gap request must be disabled (SD_HCTL[16] SBGR bit =0) before setting this bit.
0
No affect
1
Transfer restart
Stop at block gap request. This bit is used to stop executing a transaction at the next block gap.
The transfer can restart with a continue request (SD_HCTL[17] CR bit) or during a suspend/resume
sequence. In case of read transfer, the card must support read wait control. In case of write
transfer, the host driver shall set this bit after all block data written. Until the transfer completion
(SD_STAT[1] TC bit set to 1), the host driver shall leave this bit set to 1.If this bit is set, the local
host shall not write to the data register (SD_DATA).
0
Transfer mode
1
Stop at block gap
0
Reserved bit field. Do not write any value.
SD bus voltage select (All cards). The host driver should set these bits to select the voltage level for
the card according to the voltage supported by the system (SD_CAPA[26] VS18 bit, SD_CAPA[25]
VS30 bit, SD_CAPA[24] VS33 bit) before starting a transfer.
5h
1.8 V (Typical)
6h
3.0 V (Typical)
7h
3.3 V (Typical)
SD bus power. Before setting this bit, the host driver shall select the SD bus voltage
(SD_HCTL[11:9] SDVS bits). If the host controller detects the No card state, this bit is automatically
cleared to 0. If the module is power off, a write in the command register (SD_CMD) will not start the
transfer. A write to this bit has no effect if the selected SD bus voltage is not supported according to
capability register (SD_CAPA[VS*]).
0
Power off
1
Power on
Card Detect Signal Selection. This bit selects source for the card detection. When the source for
the card detection is switched, the interrupt should be disabled during the switching period by
clearing the Interrupt Status/Signal Enable register in order to mask unexpected interrupt being
caused by the glitch. The Interrupt Status/Signal Enable should be disabled during over the period
of debouncing.
0
SDCD# is selected (for normal use).
1
The Card Detect Test Level is selected (for test purposes).
Card Detect Test Level. This bit is enabled while the Card Detect Signal Selection is set to 1 and it
indicates card inserted or not.
0
No card
1
Card inserted.
0
Reserved bit field. Do not write any value.
DMA Select. One of the supported DMA modes can be selected. The host driver shall check
support of DMA modes by referencing the Capabilities register. Use of selected DMA is determined
by DMA Enable of the Transfer Mode register.
This register is only meaningful when MADMA_EN is set to 1. When MADMA_EN is cleared to 0
the bit field is read only and returned value is 0.
0
Reserved
1h
Reserved
2h
32-bit Address ADMA2 is selected.
3h
Reserved
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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