Table of Contents
Advertisement
www.ti.com
13.3.2.2 Configuration Accesses
As an endpoint, the PCIESS can only be a target of configuration accesses from upstream. Until the
link is established and APP_RETRY_EN is disabled, the PCIESS will not respond to configuration
accesses. When enabled, the PCIESS will respond to configuration accesses automatically and these
accesses do not get relayed to the master interface on the device interconnect side.
End point is not capable to accessing configuration space of devices other than its own. The system
software can initialize the read only fields in PCIESS Configuration Space via the slave port before the
link training has been initiated. Once the configuration is complete by the PCI Express Root Complex,
the system software should not modify the PCIESS configuration parameters. There is no explicit
prevention mechanism in hardware to disallow such accesses though.
13.3.2.3 Memory Accesses
There are two types of Memory Accesses – inbound and outbound memory accesses.
An inbound access is typically initiated by a Root Complex port or by another End Point that is reaching
the PCIESS via a PCI Express switch that supports peer-to-peer access. In either case, the incoming
PCIe transaction results in an access on the PCIESS master port. The response to the such accesses
is relayed back to the originating PCIe device.
In an outbound access, a DMA module or a host CPU initiates a read/write access on the PCIESS
Slave port. This request is converted into a PCIe memory read/write transaction over the PCIE link.
Once the PCIESS receives completion from the remote device, it generates a completion on the OCP
slave port. The software/hardware that initiates the request on the slave port must perform it in a
memory region that has been determined previously through software protocols. For example, the
software may get information about applicable memory regions from the software that is running on the
Root Complex device.
13.3.2.4 I/O Accesses
IO Accesses are not supported in PCIESS operating as a PCIe End Point.
13.4 Registers
13.4.1 Accessing Read-only Registers in Configuration Space
Some of the register fields provided in the configuration space can be written to prior to bus
enumeration via the slave interface of PCIESS. Note that the hardware does not prevent modification of
read only field after bus enumeration but it is strongly advised that read only fields not be written once
the bus enumeration is complete.
In addition, the BAR Mask registers can also be programmed by first enabling the DBI_CS2 bit and
then performing writes on the BAR registers. The BAR mask registers are overlaid on BAR registers.
For the BAR mask registers to be writable, the respective BAR must first be enabled.
13.4.2 Accessing EP Application Registers from PCIe RC
The application registers are also mapped at 2K and above address, in the configuration space. The
RC software can access these registers over PCIe link provided the registers are programmed to some
default values by the BOOT code in the PCIESS host device that enables link training and TLP
exchange.
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Preliminary
Peripheral Component Interconnect Express (PCIe)
© 2011, Texas Instruments Incorporated
Registers
1305
Advertisement
Table of Contents
