Texas Instruments TMS320C6A816 Series Technical Reference Manual page 996

Registers
Table 9-33. Interrupt SD Enable Register (SD_IE) Field Descriptions (continued)
Bit Field
19 CIE_ENABLE
18 CEB_ENABLE
17 CCRC_ENABLE
16 CTO_ENABLE
15 NULL
14-11 Reserved
10 BSR_ENABLE
9 OBI_ENABLE
8 CIRQ_ENABLE
7 CREM_ENABLE
6 CINS_ENABLE
5 BRR_ENABLE
4 BWR_ENABLE
3 DMA_ENABLE
2 BGE_ENABLE
996
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Preliminary
Value Description
Command index error interrupt enable
0 Masked
1 Enabled
Command end bit error interrupt enable
0 Masked
1 Enabled
Command CRC error interrupt enable
0 Masked
1 Enabled
Command timeout error interrupt enable
0 Masked
1 Enabled
0 Fixed to 0. The host driver shall control error interrupts using the Error Interrupt Signal Enable
register. Writes to this bit are ignored.
0 Reserved bit field. Do not write any value.
Boot Status Interrupt Enable A write to this register when SD_CON[BOOT] is cleared to 0 is
ignored.
0 Masked
1 Enabled
Out-of-band interrupt enable A write to this register when SD_CON[14] OBIE is cleared to 0 is
ignored.
0 Masked
1 Enabled
Card interrupt enable. A clear of this bit also clears the corresponding status bit. During 1-bit mode,
if the interrupt routine does not remove the source of a card interrupt in the SDIO card, the status
bit is reasserted when this bit is set to 1. This bit must be set to 1 when entering in smart idle mode
to enable system to identity wake-up event and to allow controller to clear internal wake-up source.
0 Masked
1 Enabled
Card Removal interrupt Enable This bit must be set to 1 when entering in smart idle mode to enable
system to identity wake-up event and to allow controller to clear internal wake-up source.
0 Masked
1 Enabled
Card Insertion interrupt Enable This bit must be set to 1 when entering in smart idle mode to enable
system to identity wake-up event and to allow controller to clear internal wake-up source.
0 Masked
1 Enabled
Buffer read ready interrupt enable
0 Masked
1 Enabled
Buffer write ready interrupt enable
0 Masked
1 Enabled
DMA interrupt enable
0 Masked
1 Enable
Block gap event interrupt enable
0 Masked
1 Enabled
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SPRUGX9 – 15 April 2011
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