Table of Contents
Advertisement
www.ti.com
10.3.7 Pin Data Clear Register (PDCLR)
The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only.
Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and, if PFUNC = 1 (GPIO function)
and PDIR = 1 (output), drives a logic low on the pin. PDCLR is useful for a multitasking system
because it allows you to clear to a logic low only the desired pin(s) within a system without affecting
other I/O pins controlled by the same McASP. The PDCLR is shown in
Table
10-16.
Writing to Reserved Bits
Writing a value other than 0 to reserved bits in this register may cause
improper device operation.
31
30
AFSR
AHCLKR
R/W-0
R/W-0
23
7
6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Preliminary
CAUTION
Figure 10-44. Pin Data Clear Register (PDCLR)
29
28
ACLKR
AFSX
R/W-0
R/W-0
Reserved
R-0
5
4
AXR5
AXR4
R/W-0
R/W-0
© 2011, Texas Instruments Incorporated
Figure 10-44
27
26
AHCLKX
ACLKX
R/W-0
R/W-0
3
2
AXR3
AXR2
R/W-0
R/W-0
Multichannel Audio Serial Port (McASP)
Registers
and described in
25
24
AMUTE
Reserved
R/W-0
R-0
8
1
0
AXR1
AXR0
R/W-0
R/W-0
1081
Advertisement
Table of Contents
