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17.2.4.2 Write Non-Posted
This mode is functional regardless of the ratio between the OCP interface frequency and the functional
clock frequency. Recommended functional frequency range is freq (timer) >= freq (OCP)/4.
This mode is used if TSICR (POSTED bit) is cleared to 0 in the timer control register.
This mode uses a non posted-write scheme to update any internal register. That means the write
transaction will not be acknowledged on the OCP interface, until the effective write operation occurs,
after the resynchronisation in the timer clock domain. The drawback is that both the interconnect
system and the CPU are stalled during this period.
•
The latency of the interrupt serving is increased, as the interconnect system and CPU are stalled.
•
An interconnect logic, including time-out logic to detect erroneous transactions, can generate an
unwanted system abort event.
The stall period is defined as the interval between the non-posted write access request and the rise of
the command accept signal and can be quantified:
T (stall max.) = 3 OCP clock + 2.5 TIMER clock
The time when the write accomplishes is:
T (write accomplish) = 1 OCP clock + 2.5 TIMER clock
A register read following a write to the same register is always coherent.
17.2.5 Read Registers Access
17.2.5.1 Read Posted
This mode can be used only if the functional frequency range is freq (timer) < freq (OCP)/4.
This mode is used if TSICR (POSTED bit) is set to 1 in the timer control register.
This mode uses a posted-read scheme, for reading any internal register. The read transaction is
immediately acknowledged on the OCP interface, and the value to be read has been previously
resynchronised. This has the advantage of not stalling either the interconnect system, or the CPU that
requested the read transaction.
17.2.5.2 Read Non-Posted
This mode is functional whatever the ratio between the OCP interface frequency and the functional
clock frequency. Recommended functional frequency range is freq (timer) >= freq (OCP)/4.
This mode is used if TSICR (POSTED bit) is cleared to 0 in the timer control register.
This mode uses a non posted-read scheme, for reading any internal register. The read transaction will
not be acknowledged on the OCP interface, until the effective read operation occurs, after the
resynchronisation in the timer clock domain. The drawback is that both the interconnect system and the
CPU are stalled during this period.
•
The latency of the interrupt serving is increased, as the interconnect system and the CPU are
stalled.
•
An interconnect system including time-out logic to detect erroneous transactions can generate an
unwanted system abort event.
This mode only applies only to three registers: TCRR, TCAR1 and TCAR2, which need
resynchronisation from functional to OCP clock domains.
The stall period is defined as the interval between the non-posted read access request and the rise of
the command accept signal and can be quantified:
T (stall max.) = 3 OCP clock + 2.5 TIMER clock
The time when the value is sampled is:
T (read sample) = 1 OCP clock + 2.5 TIMER clock
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Architecture
1643
Timers
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