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10.2.10.1.3 Data Format
For each transmit and receive data:
•
Internal numeric representation (integer, Q31 fraction)?
•
I2S or DIT (transmit only)?
•
Time slot delay (0, 1, or 2 bit)?
•
Alignment (left or right)?
•
Order (MSB first, LSB first)?
•
Pad (if yes, pad with what value)?
•
Slot size?
•
Rotate?
•
Mask?
10.2.10.1.4 Data Transfers
•
Internal: DMA or CPU?
•
External: TDM or burst?
•
Bus: configuration bus (CFG) or data port (DAT)?
10.2.10.2 Transmit/Receive Section Initialization
You must follow the following steps to properly configure the McASP. If external clocks are used, they
should be present prior to the following initialization steps.
1. Reset McASP to default values by setting GBLCTL = 0.
2. Configure all McASP registers except GBLCTL in the following order:
(a) Power down and emulation management: PWRDEMU.
(b) Receive registers: RMASK, RFMT, AFSRCTL, ACLKRCTL, AHCLKRCTL, RTDM, RINTCTL,
RCLKCHK. If external clocks AHCLKR and/or ACLKR are used, they must be running already
for proper synchronization of the GBLCTL register.
(c) Transmit registers: XMASK, XFMT, AFSXCTL, ACLKXCTL, AHCLKXCTL, XTDM, XINTCTL,
XCLKCHK. If external clocks AHCLKX and/or ACLKX are used, they must be running already for
proper synchronization of the GBLCTL register.
(d) Serializer registers: SRCTL[n].
(e) Global registers: Registers PFUNC, PDIR, DITCTL, DLBCTL, AMUTE. Note that PDIR should
only be programmed after the clocks and frames are set up in the steps above. This is because
the moment a clock pin is configured as an output in PDIR, the clock pin starts toggling at the
rate defined in the corresponding clock control register. Therefore you must ensure that the clock
control register is configured appropriately before you set the pin to be an output. A similar
argument applies to the frame sync pins. Also note that the reset state for the transmit
high-frequency clock divide register (HCLKXDIV) is divide-by-1, and the divide-by-1 clocks are
not gated by the transmit high-frequency clock divider reset enable (XHCLKRST).
(f) DIT registers: For DIT mode operation, set up registers DITCSRA[n], DITCSRB[n], DITUDRA[n],
and DITUDRB[n].
3. Start the respective high-frequency serial clocks AHCLKX and/or AHCLKR. This step is necessary
even if external high-frequency serial clocks are used:
(a) Take the respective internal high-frequency serial clock divider(s) out of reset by setting the
RHCLKRST bit for the receiver and/or the XHCLKRST bit for the transmitter in GBLCTL. All
other bits in GBLCTL should be held at 0.
(b) Read back from GBLCTL to ensure the bit(s) to which you wrote are successfully latched in
GBLCTL before you proceed.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Multichannel Audio Serial Port (McASP)
Architecture
1059
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