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12.2.3.5 Master Receive-Only Mode
This mode avoids the CPU to refill the transmitter register (minimizing data movement) when only
reception is meaningful.
The master receive mode is programmable per channel (bits TRM of the register (I)CONF).
The master receive only mode enables channel scheduling only on empty state of the receiver register.
Rule 1 and Rule 3, defined above, are applicable in this mode.
Rule 2, defined above, is not applicable: In master receive only mode, after the first loading of the
transmitter register of the enabled channel, the transmitter register state is maintained as full. The
content of the transmitter register is always loaded into the shift register, at the time of shift register
assignment. So, after the first loading of the transmitter register, the bits TX_empty and TX_underflow,
in the MCSPI_IRQSTATUS register are never set in this mode.
The status of the serialization completion is given by the bit EOT of the register MCSPI_CH(I)STAT.
The bit RX_full in the MCSPI_IRQSTATUS register is set when a received data is loaded from the shift
register to the receiver register. This bit is meaningless when using the Buffer for this channel.
The built-in FIFO is available in this mode and can be configured with FFER bit field in the
MCSPI_CH(I)CONF register, then the FIFO is seen as a unique FFNBYTE bytes buffer.
12.2.3.6 Single-Channel Master Mode
When the SPI is configured as a master device with a single enabled channel, the assertion of the
SPIM_CSX signal can be controlled in two different ways:
•
In 3 pin mode : MCSPI_MODULCTRL[1] PIN34 and MCSPI_MODULCTRL[0] SINGLE bit are set to
1, the controller transmit SPI word as soon as transmit register or FIFO is not empty.
•
In 4 pin mode : MCSPI_MODULCTRL[1] PIN34 bit is cleared to 0 and MCSPI_MODULCTRL[0]
SINGLE bit is set to 1, SPIEN assertion/deassertion controlled by Software. (See
using the MCSPI_CHxCONF[20] FORCE bit.
12.2.3.6.1 Programming Tips When Switching to Another Channel
When a single channel is enabled and data transfer is ongoing:
•
Wait for completion of the SPI word transfer (bit EOT of the register MCSPI_CH(I)STAT is set)
before disabling the current channel and enabling a different channel.
•
Disable the current channel first, and then enable the other channel.
12.2.3.6.2 Keep SPIEN Active Mode (Force SPIEN)
Continuous transfers are manually allowed by keeping the SPIEN signal active for successive SPI
words transfer. Several sequences (configuration/enable/disable of the channel) can be run without
deactivating the SPIEN line. This mode is supported by all channels and any master sequence can be
used (transmit-receive, transmit-only, receive-only).
Keeping the SPIEN active mode is supported when:
•
A single channel is used (bit MCSPI_MODULCTRL[Single] is set to 1).
•
Transfer parameters of the transfer are loaded in the configuration register (MCSPI_CH(I)CONF) in
the appropriate channel.
The state of the SPIEN signal is programmable.
– Writing 1 into the bit FORCE of the register MCSPI_CH(I)CONF drives high the SPIEN line when
MCSPI_CHCONF(I)[EPOL] is set to zero, and drives it low when MCSPI_CHCONF(I)[EPOL] is
set.
– Writing 0 into the bit FORCE of the register MCSPI_CH(I)CONF drives low the SPIEN line when
MCSPI_CHCONF(I)[EPOL] is set to zero, and drives it high when MCSPI_CHCONF(I)[EPOL] is
set.
•
A single channel is enabled (MCSPI_CH(I)CTRL[En] set to 1) . The first enabled channel activates
the SPIEN line.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Section
Multichannel Serial Port Interface (McSPI)
Architecture
12.2.3.6.1)
1225
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