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Architecture
In addition, the software drivers for downstream devices must ensure that the data transaction that is
expected to complete before interrupt is triggered in RC device's CPU has completed. Since PCIe write
transactions are posted, it is not necessary that a write from EP to system memory in RC has
completed before a write to MSI interrupt generation register has completed. This could create a
potential race condition.
It is optional to support Legacy Interrupts in PCI Express (non-legacy) devices.
13.2.10 Firewall
The device has built in security feature where access to secure targets can only be available through
authorized initiators. PCIESS when operating as a target (that is, PCIESS is the initiator of transactions
accessing external PCIe components) possess this capability. The initiators, Cortex™-A8 or EDMA,
have to be authorized to access PCIESS. The access permission is given according to the read and
writes permission register setting in the Secure Target Security Firewall.
13.2.11 DMA Support
The PCIESS has no built in DMA and makes use of the EDMA to move data in and out of the PCIESS
with out the need of the CPU intervention. EDMA is only used when PCIESS is the initiator of a
transaction and accessing other PCIe component. When another PCIe component is accessing a
resource within the PCIESS, the PCIe in this case acts as a master and it makes use of the master port
to directly access the necessary resource requiring no need for the EDMA usage. For details on EDMA,
please consult the EDMA Peripheral Guide.
As an initiator only Cortex™-A8 and EDMA can be used to move data in and out of the device
resource. As a master (that is, external PCIe component accessing device resource), it is capable of
accessing DDR (via DMM), Async EMIF (GPMC), C674x L2 Memory, and On-Chip Memory.
NOTE: Master/Slave reference here does not mean RC/EP mode. As an RC or EP, the PCIESS
can act as both Master and Slave. It means as to who is generating the request. If the
PCIESS is generating a request, it means that an external PCIe component is the actual
entity generating the request and the PCIESS is now regarded as a Master. If the
PCIESS is accessing external PCIe component, the PCIESS is regarded as a slave and
only Cortex™-A8 or EDMA is capable of moving data in and out internal resource.
13.2.11.1 DMA Support in RC Mode
When operating in Root Complex mode, the EDMA controller can perform DMA transfer between
device internal resource and any remote device located on the PCI Express fabric. The memory
address of such devices is available to the software via the PCI Express bus enumeration procedure. In
addition, the PCIe subsystem has a provision to perform memory address translation on outbound
requests. Thus, the software is able to map different memory regions in its memory map to correspond
to different addresses (and different access types) on the PCI Express side.
There are bandwidth implications of using an external DMA. If the PCIe core has been programmed to
establish a link in PCIe 2.5 Gbps rate, then the DMA controller that drives PCIESS Slave Port must be
able to write/read data at about 85% of 2 Gbps bandwidth per PCIe link. For a PCIe link speed of 5.0
Gbps, the DMA controller must be able to provide bandwidth of about 85% of 4 Gbps per PCIe link.
In addition, the master port on PCIe port can issue read/write accesses that have been initiated by
remote PCI Express device. The interconnect fabric should provide sufficient capacity to serve 85% of 2
Gbps (4 Gbps if operating in Gen2) per PCIe link in each direction.
13.2.11.2 DMA Support in EP Mode
When operating as a PCIe End Point, the device will be located in PCIe memory map at location
programmed in the Base Address Registers by the PCIe Root device. In End Point mode, the PCIESS
provides address translation functionality. It is possible to map IO, Config and Memory accesses
originating on PCI Express side to memory accesses with different address on the OCP side. These
address ranges are configurable through application registers.
1296
Peripheral Component Interconnect Express (PCIe)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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