Fifo Control Register (Fcr) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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19.3.9 FIFO Control Register (FCR)
The FIFO Control Register (FCR) is shown in
15
7 6
RX_FIFO_TRIG
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Bit Field
15-8 Reserved
7-6 RX_FIFO_TRIG
5-4 TX_FIFO_TRIG
3 DMA_MODE
2 TX_FIFO_CLEAR
1 RX_FIFO_CLEAR
0 FIFO_EN
SPRUGX9 – 15 April 2011
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Preliminary
Figure 19-36. FIFO Control Register (FCR)
5 4
TX_FIFO_TRIG
W-0
Table 19-18. FIFO Control Register (FCR) Field Descriptions
Value Description
0 Reserved.
0-3h Sets the trigger level for the RX FIFO:
If SCR[7] = 0 and TLR[7:4] ≠ 0000, RX_FIFO_TRIG is not considered.
If SCR[7] = 1, RX_FIFO_TRIG is 2 LSB of the trigger level (1 to 63 on 6 bits) with the granularity 1.
If SCR[7] = 0 and TLR[7:4] = 0000:
0 8 characters
1h 16 characters
2h 56 characters
3h 60 characters
0-3h Can be written only if EFR[4] = 1.
Sets the trigger level for the TX FIFO:
If SCR[6] = 0 and TLR[3:0] ≠ 0000, TX_FIFO_TRIG is not considered.
If SCR[6] = 1, TX_FIFO_TRIG is 2 LSB of the trigger level (1 to 63 on 6 bits) with a granularity of 1.
If SCR[6] = 0 and TLR[3:0] = 0000:
0 8 characters
1h 16 characters
2h 32 characters
3h 56 characters
Can be changed only when the baud clock is not running (DLL and DLH cleared to 0).
If SCR[0] = 0, this register is considered.
0 DMA_MODE 0 (No DMA).
1 DMA_MODE 1 (UART_NDMA_REQ[0] in TX, UART_NDMA_REQ[1] in RX).
0 No change.
1 Clears the transmit FIFO and resets its counter logic to 0. Returns to 0 after clearing FIFO.
0 No change.
1 Clears the receive FIFO and resets its counter logic to 0. Returns to 0 after clearing FIFO.
Can be changed only when the baud clock is not running (DLL and DLH cleared to 0).
0 Disables the transmit and receive FIFOs. The transmit and receive holding registers are 1-byte
FIFOs.
1 Enables the transmit and receive FIFOs. The transmit and receive holding registers are 64-byte
FIFOs.
© 2011, Texas Instruments Incorporated
Figure 19-36 and described in
Reserved
R-0
3 2
DMA_MODE TX_FIFO_CLEAR
W-0 W-0
Registers
Table 19-18.
8
1 0
RX_FIFO_CLEAR FIFO_EN
W-0 W-0
1721
UART/IrDA/CIR Module