Texas Instruments TMS320C6A816 Series Technical Reference Manual page 894

C6-integra dsp+arm processors
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Registers
Table 7-29. System Test Register (I2C_SYSTEST) Field Descriptions (continued)
Bit
Field
2
SCL_O
1
SDA_I
0
SDA_O
894
Inter-Integrated Circuit (I2C) Controller Module
Preliminary
Value
Description
SCL line drive output value. In normal functional mode (ST_EN = 0), this bit is don't care. It
always reads 0 and a write is ignored. In system test mode (ST_EN = 1 & TMODE = 11), a 0
forces a low level on the SCL line and a 1 puts the I2C output driver to a high-impedance
state.
Read:0
Forces 0 on the SCL data line
Read:1
SCL output driver in high-impedance state
Value after reset is low.
SDA line sense input value. In normal functional mode (ST_EN = 0), this read-only bit always
reads 0. In system test mode (ST_EN = 1 & TMODE = 11), this read-only bit returns the
logical state taken by the SDA line (either 1 or 0).
Read:0
Read 0 from SDA line
Read:1
Read 1 from SDA line
Value after reset is low.
SDA line drive output value. In normal functional mode (ST_EN = 0), this bit is don't care. It
reads as 0 and a write is ignored. In system test mode (ST_EN = 1 & TMODE = 11), a 0
forces a low level on the SDA line and a 1 puts the I2C output driver to a high-impedance
state.
0
Write 0 to SDA line
1
Write 1 to SDA line
Value after reset is low.
© 2011, Texas Instruments Incorporated
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SPRUGX9 – 15 April 2011
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