States Of A Logic Area In A Power Domain; States Of A Memory Area In A Power Domain; Power Domain Control And Status Registers - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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To minimize device power consumption, the modules are grouped into power domains. A power
domain can be split into a logic area
State
On
Off
State
On
Off
14.1.4.2 Power Domain Management
The power manager associated with each power domain is assigned the task of managing the domain
power transitions. It ensures that all hardware conditions are satisfied before it can initiate a power
domain transition from a source to a target power state.
Register/Bit Field
PM_<Power domain>_PWRSTCTRL[1:0]
POWERSTATE
PM_<Power domain>_PWRSTST[1:0]
POWERSTATEST
PM_<Power domain>_PWRSTST[2]
LOGICSTATEST
PM_<Power domain>_PWRSTST[5:4]
MEMSTATEST
14.1.4.3 Power-Management Techniques
The following section describes the state-of-the-art power-management techniques supported by the
device.
14.1.4.3.1 Adaptive Voltage Scaling
Adaptive voltage scaling (AVS) is a power-management technique based in Smart Reflex that is used
for automatic control of the operating voltages of the device to reduce active power consumption. With
Smart Reflex, power-supply voltage is adapted to silicon performance, either statically (based on
performance points predefined in the manufacturing process of a given device) or dynamically (based
on the temperature-induced real-time performance of the device). A comparison of these predefined
performance points to the real-time on-chip measured performance determines whether to raise or
lower the power-supply voltage. AVS achieves the optimal performance/power trade-off for all devices
across the technology process spectrum and across temperature variation. The device voltage is
automatically adapted to maintain performance of the device.
SPRUGX9 – 15 April 2011
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Preliminary
(Table 14-10) and a memory area
Table 14-10. States of a Logic Area in a Power Domain
Description
Logic is fully powered
Logic power switches are off. All the logic (DFF) is lost.
Table 14-11. States of a Memory Area in a Power Domain
Description
The memory array is powered and fully functional.
The memory array is powered down.
Table 14-12. Power Domain Control and Status Registers
Type
Control
Status
Status
Status
© 2011, Texas Instruments Incorporated
(Table
Description
Selects the target power state of the power domain among OFF
or ON
Identifies the current state of the power domain. It can be OFF
or ON
Identifies the current state of the logic area in the power domain.
It can be OFF or ON.
Identifies the current state of the memory area in the power
domain. It can be OFF or ON.
Power, Reset, and Clock Management (PRCM) Module
Introduction
14-11).
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