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14.7.11.26 CM_ALWON_TIMER_2_CLKCTRL Register
The CM_ALWON_TIMER_2_CLKCTRL register manages the TIMER_2 clocks. It is shown and
described in the figure and table below.
31
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-121. CM_ALWON_TIMER_2_CLKCTRL Register Descriptions
Bit
Field
31-18
Reserved
17-16
IDLEST
15-2
Reserved
1-0
MODULEMODE
SPRUGX9 – 15 April 2011
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Preliminary
Figure 14-106. CM_ALWON_TIMER_2_CLKCTRL Register
18 17
16 15
IDLEST
R-3h
Value
Description
0
Reserved
Module idle status.
0
Module is fully functional, including OCP
1h
Module is performing transition: wakeup, or sleep, or sleep abortion
2h
Module is in Idle mode (only OCP part). It is functional if using separate
functional clock
3h
Module is disabled and cannot be accessed
0
Reserved
Control the way mandatory clocks are managed.
0
Module is disabled by software. Any OCP access to module results in an
error, except if resulting from a module wakeup (asynchronous wakeup).
1h
Reserved
2h
Module is explicitly enabled. Interface clock (if not used for functions) may
be gated according to the clock domain state. Functional clocks are
guarantied to stay present. As long as in this configuration, power domain
sleep transition cannot happen.
3h
Reserved
© 2011, Texas Instruments Incorporated
Reserved
R-0
Power, Reset, and Clock Management (PRCM) Module
Registers
2
1
0
MODULEMODE
R/W-0
1503
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