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Table 9-29. Present State Register (SD_PSTATE) Field Descriptions (continued)
Bit
Field
16
15-12
Reserved
11
BRE
10
BWE
9
RTA
8
WTA
7-3
Reserved
2
DLA
1
DATI
SPRUGX9 – 15 April 2011
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Preliminary
Value
Description
Card inserted. This bit is the debounced value of the card detect input pin (SDCD). An inactive
to active transition of the card detect input pin (SDCD) will generate a card insertion interrupt
(SD_STAT[CINS]). A active to inactive transition of the card detect input pin (SDCD) will
generate a card removal interrupt (SD_STAT[REM]). This bit is not affected by a software
reset.
Read 0
If SD_CON[CDP] is cleared to 0 (default), no card is detected. The card may have been
removed from the card slot. If SD_CON[CDP] is set to 1, the card has been inserted.
Read 1
If SD_CON[CDP] is cleared to 0 (default), the card has been inserted from the card slot. If
SD_CON[CDP] is set to 1, no card is detected. The card may have been removed from the
card slot.
0
Reserved bit field. Do not write any value.
Buffer read enable. This bit is used for non-DMA read transfers. It indicates that a complete
block specified by SD_BLK[10:0] BLEN bits has been written in the buffer and is ready to be
read. It is cleared to 0 when the entire block is read from the buffer. It is set to 1 when a block
data is ready in the buffer and generates the Buffer read ready status of interrupt
(SD_STAT[5] BRR bit).
Read 0
Read BLEN bytes disable
Read 1
Read BLEN bytes enable. Readable data exists in the buffer.
Buffer Write enable. This status is used for non-DMA write transfers. It indicates if space is
available for write data.
Read 0
There is no room left in the buffer to write BLEN bytes of data.
Read 1
There is enough space in the buffer to write BLEN bytes of data.
Read transfer active. This status is used for detecting completion of a read transfer. It is set to
1 after the end bit of read command or by activating a continue request (SD_HCTL[17] CR bit)
following a stop at block gap request. This bit is cleared to 0 when all data have been read by
the local host after last block or after a stop at block gap request.
Read 0
No valid data on the SD_DAT lines.
Read 1
Read data transfer on going.
Write transfer active. This status indicates a write transfer active. It is set to 1 after the end bit
of write command or by activating a continue request (SD_HCTL[17] CR bit) following a stop
at block gap request. This bit is cleared to 0 when CRC status has been received after last
block or after a stop at block gap request.
Read 0
No valid data on the SD_DAT lines.
Read 1
Write data transfer on going.
0
Reserved bit field. Do not write any value.
SD_DAT line active. This status bit indicates whether one of the SD_DAT lines is in use.
In the case of read transactions (card to host)This bit is set to 1 after the end bit of read
command or by activating continue request SD_HCTL[17] CR bit. This bit is cleared to 0 when
the host controller received the end bit of the last data block or at the beginning of the read
wait mode.
In the case of write transactions (host to card)This bit is set to 1 after the end bit of write
command or by activating continue request SD_HCTL[17] CR bit.
This bit is cleared to 0 on the end of busy event for the last block; host controller must wait 8
clock cycles with line not busy to really consider not "busy state" or after the busy block as a
result of a stop at gap request.
Read 0
SD_DAT line inactive
Read 1
SD_DAT line active
Command inhibit (SD_DAT). This status bit is generated if either SD_DAT line is active
(SD_PSTATE[2] DLA bit) or Read transfer is active (SD_PSTATE[9] RTA bit) or when a
command with busy is issued. This bit prevents the local host to issue a command.
A change of this bit from 1 to 0 generates a transfer complete interrupt (SD_STAT[1] TC bit).
Read 0
Issuing of command using the SD_DAT lines is allowed
Read 1
Issuing of command using SD_DAT lines is not allowed
© 2011, Texas Instruments Incorporated
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Registers
983
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