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Registers
19.3.4 Interrupt Enable Register (IER) - IrDA Mode
The IrDA interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are
8 types of interrupt in these modes, received EOF, LSR interrupt, TX status, status FIFO interrupt, RX
overrun, last byte in RX FIFO, THR interrupt, and RHR interrupt. Each interrupt can be
enabled/disabled individually. The IrDA interrupt enable register (IER) is shown in
described in
Table
NOTE: The TXSTATUSIT interrupt reflects two possible conditions. The MDR2[0] bit should be
read to determine the status in the event of this interrupt.
15
7
6
EOFIT
LINESTSIT
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-13. IrDA Interrupt Enable Register (IER) Field Descriptions
Bit
Field
15-8
Reserved
7
EOFIT
6
LINESTSIT
5
TXSTATUSIT
4
STSFIFOTRIGIT
3
RXOVERRUNIT
2
LASTRXBYTEIT
1
THRIT
0
RHRIT
1716
UART/IrDA/CIR Module
Preliminary
19-13.
Figure 19-31. IrDA Interrupt Enable Register (IER)
5
4
TXSTATUSIT
STSFIFOTRIGIT
R/W-0
R/W-0
Value
Description
0
Reserved.
0
Disables the received EOF interrupt.
1
Enables the received EOF interrupt.
0
Disables the receiver line status interrupt.
1
Enables the receiver line status interrupt.
0
Disables the TX status interrupt.
1
Enables the TX status interrupt.
0
Disables status FIFO trigger level interrupt.
1
Enables status FIFO trigger level interrupt.
0
Disables the RX overrun interrupt.
1
Enables the RX overrun interrupt.
0
Disables the last byte of frame in RX FIFO interrupt.
1
Enables the last byte of frame in RX FIFO interrupt.
0
Disables the THR interrupt.
1
Enables the THR interrupt.
0
Disables the RHR interrupt.
1
Enables the RHR interrupt.
© 2011, Texas Instruments Incorporated
Reserved
R-0
3
RXOVERRUNIT
LASTRXBYTEIT
R/W-0
www.ti.com
Figure 19-31
and
2
1
THRIT
R/W-0
R/W-0
SPRUGX9 – 15 April 2011
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8
0
RHRIT
R/W-0
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