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Table 9-30. Control Register (SD_HCTL) Field Descriptions (continued)
Bit
Field
2
HSPE
1
DTW
0
Reserved
SPRUGX9 – 15 April 2011
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Preliminary
Value
Description
High Speed Enable. Before setting this bit, the Host Driver shall check the High Speed Support in
the Capabilities register. If this bit is cleared to 0 (default), the Host Controller outputs CMD line and
DAT lines at the falling edge of the SD Clock.
If this bit is set to 1, the Host Controller outputs CMD line and DAT lines at the rising edge of the
SD Clock. This bit shall not be set when dual data rate mode is activated in SD_CON[DDR].
0
Normal speed mode
1
High speed mode
Data transfer width. This bit must be set following a valid SET_BUS_WIDTH command (ACMD6)
with the value written in bit 1 of the argument. Prior to this command, the SD card configuration
register (SCR) must be verified for the supported bus width by the SD card.
0
1-bit Data width (SD_DAT0 used)
1
4-bit Data width (SD_DAT[3:0] used)
0
Reserved bit field. Do not write any value.
© 2011, Texas Instruments Incorporated
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Registers
987
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