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Protocol Description(s)
The sequence of events will begin, as with all requests, when the software receives an endpoint 0
interrupt. The RXPKTRDY bit of PERI_CSR0 will also have been set. The 8-byte command should then
be read from the Endpoint 0 FIFO and decoded.
As with a zero data request, the PERI_CSR0 register should then be written to set the
SERV_RXPKTRDY bit (bit 6) (indicating that the command has been read from the FIFO) but in this
case the DATAEND bit (bit 3) should not be set (indicating that more data is expected).
When a second endpoint 0 interrupt is received, the PERI_CSR0 register should be read to check the
endpoint status. The RXPKTRDY bit of PERI_CSR0 should be set to indicate that a data packet has
been received. The COUNT0 register should then be read to determine the size of this data packet.
The data packet can then be read from the endpoint 0 FIFO.
If the length of the data associated with the request (indicated by the wLength field in the command) is
greater than the maximum packet size for endpoint 0, further data packets will be sent. In this case,
PERI_CSR0 should be written to set the SERV_RXPKTRDY bit, but the DATAEND bit should not be
set.
When all the expected data packets have been received, the PERI_CSR0 register should be written to
set the SERV_RXPKTRDY bit and to set the DATAEND bit (indicating that no more data is expected).
When the host moves to the status stage of the request, another endpoint 0 interrupt will be generated
to indicate that the request has completed. No further action is required from the software, the interrupt
is just a confirmation that the request completed successfully.
If the command is an unrecognized command, or for some other reason cannot be executed, then
when it has been decoded, the PERI_CSR0 register should be written to set the SERV_RXPKTRDY bit
(bit 6) and to set the SENDSTALL bit (bit 5). When the host sends more data, the controller will send a
STALL to tell the host that the request was not executed. An endpoint 0 interrupt will be generated and
the SENTSTALL bit of PERI_CSR0 (bit 2) will be set.
If the host sends more data after the DATAEND has been set, then the controller will send a STALL. An
endpoint 0 interrupt will be generated and the SENTSTALL bit of PERI_CSR0 (bit 2) will be set.
20.3.1.1.3 Read Requests: Peripheral Mode
Read requests have a packet (or packets) of data sent from the function to the host after the 8-byte
command. Examples of Read Standard Device Requests are:
•
GET_CONFIGURATION
•
GET_INTERFACE
•
GET_DESCRIPTOR
•
GET_STATUS
•
SYNCH_FRAME
The sequence of events will begin, as with all requests, when the software receives an endpoint 0
interrupt. The RXPKTRDY bit of PERI_CSR0 (bit 0) will also have been set. The 8-byte command
should then be read from the endpoint 0 FIFO and decoded. The PERI_CSR0 register should then be
written to set the SERV_RXPKTRDY bit (bit 6) (indicating that the command has read from the FIFO).
The data to be sent to the host should then be written to the endpoint 0 FIFO. If the data to be sent is
greater than the maximum packet size for endpoint 0, only the maximum packet size should be written
to the FIFO. The PERI_CSR0 register should then be written to set the TXPKTRDY bit (bit 1)
(indicating that there is a packet in the FIFO to be sent). When the packet has been sent to the host,
another endpoint 0 interrupt will be generated and the next data packet can be written to the FIFO.
When the last data packet has been written to the FIFO, the PERI_CSR0 register should be written to
set the TXPKTRDY bit and to set the DATAEND bit (bit 3) (indicating that there is no more data after
this packet).
When the host moves to the status stage of the request, another endpoint 0 interrupt will be generated
to indicate that the request has completed. No further action is required from the software: the interrupt
is just a confirmation that the request completed successfully.
1762
Universal Serial Bus (USB)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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