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13.2.6 PCIe Loopback
The PCIe Specifications provides loopback support in two ways – through PIPE interface (Link Layer)
and second through PHY loopback capability (PHY Layer).
The PIPE Interface Loopback requires for two PCIe Devices/Components to attached to each other in a
Loopback Master and a Loopback Slave configuration. A Loopback Master is the component requesting
Loopback. A Loopback Slave is the component looping back the data. Note that, regardless with the
PCIESS role it assumes (RC or EP), it can assume a role of a Loopback Master or a Loopback Slave.
The Loopback, Loopback at the PHY Level, does not require another component.
13.2.6.1 PIPE Loopback
The procedure depends upon whether the device is operating in RC or EP Mode. In either case, the
PCIESS can be loopback master or loopback slave as outlined in PCIe specifications. Note that this
Loopback Mode cannot be used for looping back transactions. These modes are to be used with PCIe
test equipment only for symbol level loopback.
The Loopback entry procedure when PCIESS is a Loopback Master:
RC Mode
1. Set Loopback Enable in the Port Link Control Register in Port Logic Register space.
2. The link retraining sequence must be initiated by writing to Link Retrain field in the Link Control
Register in PCI Express Capabilities structure in the device's PCI Configuration Space.
EP Mode
1. Set Loopback Enable in the Port Link Control Register.
2. Force the LTSSM to be in recovery state via the Port Force Link register of the Port Logic
registers.
3. Set Force Link bit to high in Port Force Link register in Port Logic Registers.
Once this is done, devices at the ends of a PCIe link enter PCIe LTSSM Loopback state. The
initiator of loopback state is the loopback master and the other device is loopback slave. Note that it
is not possible to send TLPs in this mode and return them via the loopback state of the other device.
The Loopback entry procedure when PCIESS is a Loopback Slave:
If the PCIESS is a Loopback slave, then the incoming serial data is routed back to the originating
device from the PIPE interface as per PCIe loopback requirements. Typically, PCIe test equipment
will be used as Loopback Master and it will transition PCIESS into Loopback Slave state following
which the inbound transactions will be Loopback to the test equipment. There is no programming
required on PCIESS to enter Loopback in slave mode. PHY support is not required to use this
loopback mode.
13.2.6.2 PHY Loopback
The PHY loopback is accomplished by switching the PHY to loopback where the transmitted data is
looped back to the receive path at the PHY level. This mode can be used to perform TLP loopback
even if there is no link partner. It is, however, only possible to set up when PCIESS is used in RC
mode. This limitation is because of the fact that link training cannot occur between two upstream ports;
at least one port must be a downstream port.
The procedure is similar to the one for PIPE (Link Layer) interface but the PHY programming is used
instead. This mode is entered by configuring the SERDES configuration registers. Both the Transmit
and Receive paths must be set in loopback mode to enable PHY loopback mode.
Note that there are several other requirements for this to correctly work:
1. The PHY should be configured to operate in loopback mode before any transaction is sent out.
Recommended approach is to set loopback before link training. Otherwise, any transactions that
were not looped back will cause sequence numbers to increment on transmitter but not on receiver
and all following transactions will be dropped because of sequence number mismatch.
2. The BAR0 and BAR1 values (if programmed) should not match the address for the transaction that
is issued on slave interface. Otherwise, it will not get to the master port but to internal registers.
SPRUGX9 – 15 April 2011
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Preliminary
Peripheral Component Interconnect Express (PCIe)
© 2011, Texas Instruments Incorporated
Architecture
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