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14.5.4.1 Global Warm Reset Sequence
The following sequence describes the main chronological steps during a global warm reset sequence:
Assumptions are: Device V
released All the PLLs are locked.
•
Upon assertion of any global warm reset source: The GLOBAL_WARM_RSTACTST signal is
asserted High by the PRCM to indicate to the EMIF module that global warm reset event has
occurred. Following the assertion of the status signal, EMIF starts putting its OCP interface into the
idle state. The PRCM delays global warm reset to the device for minimum 16 L3 clock cycles until
EMI puts its OCP interface properly in idle state.
In parallel to this, the PRCM also asserts the EMIF_IDLEREQ driven to EMIF module so that EMIF
can drain all its outstanding requests and starts putting the external SDRAM memory into the
self-refresh mode. The EMIF asserts its IDLEACK high once memory is properly put in self-refresh
mode.
•
The device reset manager resets part of the device by asserting the global warm reset The external
warm reset is asserted (SYS_NRES_WARM_OUT port) but gets de-asserted after approx 30 CLKIN
cycles irrespective of SYS_WARMIN_RST state.
– All the domain warm resets are asserted
– The DPLL resets are not asserted
– The system clock, CLKIN, is running at the system clock frequency
– The registers sensitive to a warm reset are synchronously reset (PRCM registers sets)
– The PRCM cuts all the clocks not requested by the registers reset value setting
•
The global warm reset is released. The global warm reset is extended after release of the warm
reset source until all the following conditions are met:
Device reset manager counter overflowed (setup by the register PRM_RSTTIME.RSTTIME2)
Voltages are stable
•
The external warm reset is de-asserted.
•
The MPU clock is running.
•
The MPU domain is released from reset. The MPU re-boots.
NOTE: The C674x DSP, are held under reset after global warm reset by assertion of software
source of reset. Other domains such are held under reset after global warm reset until the
MPU software enables their respective interface clock.
14.5.5 MPU Subsystem POR Sequence
The power on reset must be applied when MPU SS is first powered up. Following is the detailed
description of MPU power on reset sequence.
During the initial power up sequence, the PRCM it asynchronously releases the DPLL_MAIN_RST
signal for the main PLL and. Once the main PLL reset is released, it starts the PLL initialization. The
PLL is configured in bypass mode and it provides the bypass output CLK to all the modules inside MPU
SS.
The PRCM releases the reset to INTC module inside MPUSS, i.e., it asynchronously releases the
MPU_AO_RST signal to MPUSS.
Before the MPU power on reset is de-asserted, the PRCM must ensure that the MPU CLK is running so
that MPU can be reset properly
The PRCM releases MPU_PWRN_RST and it waits until MPUSS power on Reset done i.e.
MPU_PWRN_RSTDONE signal is asserted HIGH by the MPUSS.
Following the de-assertion of MPU_PWRN_RST signal, the MPU SS de-asserts the nPORESET signal
to the Cortex™-A8 CPU and after sufficient number of MPU CLK cycles MPU SS asserts the
MPU_PWRN_RSTDONE signal high to indicate to the PRCM that synchronous power on reset
sequence is completed inside MPU SS.
SPRUGX9 – 15 April 2011
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Preliminary
is regulated at to the required voltage The system is running: Resets are
DD
© 2011, Texas Instruments Incorporated
Power, Reset, and Clock Management (PRCM) Module
Reset Management
1419
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