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Table 11-8. Analysis of the Receiver Smart Idle Behavior (continued)
CLKRM
CLKXM
1
Notes:
•
The RFSREN/XFSXEN mode is suitable for wake-up generation when both clocks (functional and
OCP) are switched off and McBSP.FSR/McBSP.FSX is configured as input. The frame sync-pulse is
asynchronously detected during idle.
•
The RSYNCERREN/XSYNCERREN mode can be used to wake-up the McBSP only by a remote
module implementing such a feature, to use this type of error in order to trigger a wake-up. This
mode requires functional clock to be active.
•
When McBSP.FSR/McBSP.FSX is configured as an output, the McBSP.FSR/ McBSP.FSX wake-up
generation makes no sense (the module cannot be in SmartIdle mode).
•
Detection of RSYNCERR/XSYNCERR during idle mode can be used only when McBSP.FSR/
McBSP.FSX is configured as an input and the remote system knows to assert such an error in order
to trigger the wake-up of the McBSP.
•
The module does not implement IRQ assertion when configured as GPIO; also a wake-up capability
in this mode is not available.
11.2.8 Programming Model
11.2.8.1 McBSP Initialization Procedure
The serial port initialization procedure is as follows:
1. Clear SPCR1_REG[0] register RRST bit, SPCR2_REG[7] register FRST bit, and SPCR2_REG[0]
register XRST bit to 0. If coming out of a global reset, this step is not required.
2. While the serial port is in the reset state, program only the McBSP configuration registers (not the
data registers) as required.
3. Wait for two clock cycles. This ensures proper internal synchronization
4. Set SPCR1_REG[0] register RRST bit and SPCR2_REG[0] register XRST bit to 1 to enable the
serial port. Make sure that as you set these reset bits, you do not modify any of the other bits in
SPCR1_REG and SPCR2_REG registers. Otherwise, you would change the configuration set in
step 2.
5. Set up data acquisition as required (such as writing to DXR_REG register).
6. Set SPCR2_REG[7] register FRST bit to 1 if internally generated frame synchronization is required.
7. Wait for two clock cycles for the receiver and transmitter to become active.
Alternatively, on write (step 1 or 5), the transmitter and receiver can be placed in or taken out of reset
by modifying the desired bit.
SPRUGX9 – 15 April 2011
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Preliminary
Behavior
1
McBSP is configured as transmit and receive master (the source clock can be CLKS or OCP).
When OCP clock is used as source clock and CLOCKACTIVITY is indicating that the OCP clock
will be switched off, or CLKS clock is used as source clock and CLOCKACTIVITY is indicating
that the functional clock is switched off, the McBSP will not acknowledge the SmartIdle request
unless:
• both transmit and receive parts are disabled (XDISABLE/RDISABLE) or under software
reset (XRST/RRST)
The SmartIdle acknowledge is asserted as soon as there is no pending DMA, interrupt request or
transmit/receive buffer threshold synchronization (only when wake-up event is set on
transmit/receive threshold reached) and the pending transmit and/or receive frames where
completed in case of transmit and/or receive disable. Note that no wakeup event will be available
in this mode since the entire McBSP and remote device activity will be frozen.
When OCP or CLKS is used as source clock and the CLOCKACTIVITY indicates that the
corresponding clock will not be switched off, the module will acknowledge the SmartIdle mode
request as soon as there is no pending DMA, interrupt request or transmit/receive buffer
threshold synchronization (only when wake-up event is set on transmit/receive threshold
reached).
© 2011, Texas Instruments Incorporated
Multichannel Buffered Serial Port (McBSP)
Architecture
1155
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