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Protocol Description(s)
20.3.2.1.3 Data Phase (OUT Data Phase) of a Control Transaction: Host Mode
For the OUT Data Phase of a control transaction
device needs to:
1. Load the data to be sent into the endpoint 0 FIFO.
2. Set the TXPKTRDY bit of HOST_CSR0 (bit 1). The controller then proceeds to send an OUT token
followed by the data from the FIFO to Endpoint 0 of the addressed device, retrying as necessary.
3. At the end of the attempt to send the data, the controller will generate an Endpoint 0 interrupt. The
software should then read HOST_CSR0 to establish whether the RXSTALL bit (bit 2), the ERROR
bit (bit 4) or the NAK_TIMEOUT bit (bit 7) has been set.
If RXSTALL bit is set, it indicates that the target has issued a STALL response.
If ERROR bit is set, it means that the controller has tried to send the OUT token and the following
data packet three times without getting any response. If NAK_TIMEOUT is set, it means that the
controller has received a NAK response to each attempt to send the OUT token, for longer than the
time set in the HOST_NAKLIMIT0 register. The controller can then be directed either to continue
trying this transaction (until it times out again) by clearing the NAK_TIMEOUT bit or to abort the
transaction by flushing the FIFO before clearing the NAK_TIMEOUT bit.
If none of RXSTALL, ERROR or NAKLIMIT is set, the OUT data has been correctly ACKed.
4. If further data needs to be sent, the software should repeat Steps 1-3.
When all the data has been successfully sent, the software should proceed to the IN Status Phase
of the Control Transaction.
1782
Universal Serial Bus (USB)
Preliminary
(Figure
20-9), the software driving the USB host
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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