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Architecture
However, Address Translation for Address Space One requires the use of one of the four Regions
(Regions[0-3]) to map accepted TLPs to Internal/Physical memory address. Four region specific
memory mapped registers exist and used by the Inbound Address Translator.
Association between regions (Regions[0-3]) and BARs is made via the corresponding IB_BARn [n=0-3]
register. IB_STARTn_HI [n = 0-3] and IB_STARTn_LO [n = 0-3] are used to hold the start address of a
64-bit PCIe Address to match, and IB_OFFSETn [n = 0-3] is used to hold the Offset for that particular
Region (note that what is referred here as offset could be viewed as the physical Memory Base
Address). Note also that for 32-bit addressing, IB_STARTn_HI[0-3] is programmed to zero.
The procedure used by the In-Bound Address Translator to perform the mapping between the PCIe
Address and Address Space One is as follows:
1. Extract the Offset: PCIe Address – (IB_STARTn_HI : IB_STARTn_LO)
2. Compute absolute OCP/Internal address: Add Base Address IB_OFFSETn to the Offset extracted
on step 1.
NOTE: When using TLPs with 64-bit addressing a pair of adjacent BARs are concatenated to
hold the 64-bit Address. This implies that BAR0 and BAR1 will hold the 64-bit Address
with BAR1 holding the high 32-bit PCIe address to match and BAR0 holding the low 32-bit
PCIe address to match. Same argument holds for BAR3, BAR4 and BAR5, BAR6 where
BAR3 and BAR5 hold the low 32-bit of the 64-bit addresses.
Example 2:
For a given 64-bit PCIe Address of 1234 5678 ABC5 0000h, that qualifies for acceptance; what
would be the corresponding mapped Internal (Physical) Device Address be? (Assume that Region 1
registers are programmed to match BAR2, BAR3 RC programmed addresses).
Further assume that application software has programmed the set of registers corresponding to
Region 1 with the values shown below.
•
IB_BAR1 = 2. This assignment associates Region 1 with BAR2, or BAR3 for 64-bit Addressing.
This value programmed as 2 associates the match between Region 1 (IB_BAR1) and
Configuration Register BAR2/BAR3.
•
IB_START1_HI = 1234 5678h
•
IB_START1_LO = ABC0 0000h
•
IB_OFFSET1 = 3340 0000h
The OCP/Internal address is computed by Subtracting the PCIe Base Address and extracting the
Offset from the PCIe Address (Address within the TLP Header) and add the resultant to the start
Address of the OCP/Internal address.
Extract the Offset from the PCIe Address:
•
Extracted Offset = PCIe address – (IB_STARTn_HI : IB_STARTn_LO) => Extracted Offset =
1234 5678 ABC5 0000h – 1234 5678 ABC0 0000h = 0005 0000h
Compute the absolute OCP/Internal address:
•
Add the extracted Offset to the Internal Base Address:
Internal/Physical Absolute Address = 3340 0000h + 0005 0000h = 3345 0000h
In example 2, PCIe Address of 1234 5678 ABC5 0000h is translated or mapped to OCP/Internal
address, 3345 0000h.
13.2.3.2.1 BAR0 Exception for In-Bound Address Translation
The memory space covered by BAR0 in inbound direction is completely dedicated to accessing the
application registers, Address Space Zero. It implies that the BAR0 cannot be remapped to any other
location but to application registers. Any remote inbound access matching the BAR0 region will
automatically be routed to these registers. It allows RC devices to control EP devices in absence of
dedicated software running on EP. For RC and EP, this mapping of BAR0 to registers allows the
message signaled interrupts to work. There is no support to disable BAR0 accesses from reaching the
application registers.
1280
Peripheral Component Interconnect Express (PCIe)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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