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Protocol Description(s)
20.3.2.2.2.1 Bulk OUT Setup: Host Mode
Before initiating any bulk OUT transactions:
•
The target function address needs to be set in the TXFUNCADDR register for the selected controller
endpoint. (TXFUNCADDR register is available for all endpoints from EP0 to EP15.)
•
The HOST_TXTYPE register for the endpoint that is to be used needs to be programmed as:
– Operating speed in the SPEED bit field (bits 7 and 6).
– Set PROT field to 10b for bulk transfer.
– Enter Endpoint Number of the target device in TENDPN field. This is the endpoint number
contained in the OUT(Tx) endpoint descriptor returned by the target device during enumeration.
•
The TXMAXP register for the controller endpoint must be written with the maximum packet size (in
bytes) for the transfer. This value should be the same as the wMaxPacketSize field of the Standard
Endpoint Descriptor for the target endpoint.
•
The HOST_TXINTERVAL register needs to be written with the required value for the NAK limit
(2-215 frames/microframes), or set to zero if the NAK timeout feature is not required.
•
The relevant interrupt enable bit in the INTRTXE register should be set (if an interrupt is required for
this endpoint).
•
The following bits of HOST_TXCSR register should be set as:
– Set the MODE bit (bit 13) to 1 to ensure the FIFO is enabled (only necessary if the FIFO is
shared with an Rx endpoint).
– Clear the FRCDATATOG bit (bit 11) to 0 to allow normal data toggle operations.
– Clear/Set AUTOSET bit (bit 15). The setting of this bit depends on the desire of the
user/application in automatically setting the TXPKTRDY bit when servicing transactions using
CPU.
Note: If DMA is needs to be used in place of the CPU, the following table displays the setting of the
core register HOST_TXCSR register in Host mode. For the CPPI DMA registers settings consult the
section on CPPI DMA within this document.
Bit Field
Bit Name
Bit 15
AUTOSET
Bit 14
ISO
Bit 13
MODE
Bit 12
DMAEN
Bit 11
FRCDATATOG
Bit 10
DMAMODE
When the endpoint is first configured, the endpoint data toggle should be cleared to 0 either by using
the DATATOGWREN bit and DATATOG bit of HOST_TXCSR (bit 9 and bit 8) to toggle the current
setting or by setting the CLRDATATOG bit of HOST_TXCSR (bit 6). This will ensure that the data
toggle (which is handled automatically by the controller) starts in the correct state. Also, if there are any
data packets in the FIFO (indicated by the FIFONOTEMPTY bit of HOST_TXCSR register (bit 1) being
set), they should be flushed by setting the FLUSHFIFO bit (bit 3 of HOST_TXCSR).
NOTE: It may be necessary to set this bit twice in succession if double buffering is enabled.
1790
Universal Serial Bus (USB)
Preliminary
Cleared to 0 if using DMA. For CPU Mode use, if AUTOSET bit is set, the TXPKTRDY
bit will be automatically set when data of the maximum packet size is loaded into the
FIFO.
Cleared to 0 for bulk mode operation.
Set to 1 to make sure the FIFO is enabled (only necessary if the FIFO is shared with an
RX endpoint)
Set to 1 to enable DMA usage; not needed if CPU is being used to service the Tx
Endpoint
Cleared to 0 to allow normal data toggle operations.
Set to 1 when DMA is used to service Tx FIFO.
© 2011, Texas Instruments Incorporated
Description
SPRUGX9 – 15 April 2011
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