Link_Cap Register - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

13.4.8.4 LINK_CAP Register

31
23 22
Reserved BW_NOTIFY_
CAP
R-0 R-0
15 14
L1_EXIT_LAT
R-6h
7
MAX_LINK_WIDTH
LEGEND: R = Read only; -n = value after reset
Bit Field
31-24 PORT_NUM
23-22 Reserved
21 BW_NOTIFY_CAP
20 DLL_REP_CAP
19 DOWN_ERR_REP_CAP
18 CLK_PWR_MGMT
17-15 L1_EXIT_LAT
14-12 LOS_EXIT_LAT
11-10 AS_LINK_PM
9-4 MAX_LINK_WIDTH
3-0 MAX_LINK_SPEED
1366
Peripheral Component Interconnect Express (PCIe)
Preliminary
Figure 13-108. LINK_CAP Register
21 20
DLL_REP_
CAP
R-0
12
LOS_EXIT_LAT
R-5h
4
R-2h
Table 13-115. LINK_CAP Register Field Descriptions
Value Description
0-FFh Port Number. Writable from internal bus interface.
0 Reserved
0 Link Bandwidth Notification Capable. Always 1 for downstream and 0 for upstream.
0 Data Link Layer Active Reporting Capable. Always 1 for downstream and 0 for
upstream.
0 Surprise Down Error Reporting Capable. Not supported. Always zero.
0 Clock Power Management. Zero for downstream ports. Writable from internal bus
interface.
0-7h L1 Exit Latency when common clock is used. Writable from internal bus interface.
0-7h L0s Exit Latency. Writable from internal bus interface.
0-3h Active State Link PM Support. Writable from internal bus interface. By default, L0s is
enabled and L1 is disabled.
0-3Fh Maximum Link Width. Writable from internal bus interface.
0-Fh Maximum Link Speed. Writable from internal bus interface.
© 2011, Texas Instruments Incorporated
PORT_NUM
R-0
19
DOWN_ERR_REP_ CLK_PWR_
CAP
R-0
11 10
AS_LINK_PM
R-1
3
MAX_LINK_SPEED
18 17
L1_EXIT_LAT
MGMT
R-0 R-6h
9
MAX_LINK_WIDTH
R-0
R-2h
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
www.ti.com
24
16
8
0