Texas Instruments TMS320C6A816 Series Technical Reference Manual page 1586

Use Cases
myCmdFis.cfisDw2SecNumLbaLowExp=0x00;
myCmdFis.cfisDw2CylLowLbaMidExp=0x00;
myCmdFis.cfisDw2CylHighLbahighExp=0x00;
myCmdFis.cfisDw2FeatureExp=0x00;
myCmdFis.cfisDw3SecCntExp=0x00;
// Invalidate for future use.
Dev28bitLbaAddress = 0xFFFFFFFF;
return(0);
}
void buildCmdFis(CommandTable *CmdSlotNum) {
// +----------+----------+--------------+-----------+
// DW0| FEATURE | COMMAND
// +----------+----------+--------------+-----------+
// DW1| DEVICE
// +----------+----------+--------------+-----------+
// DW2|FETURESexp|LBAHIGHexp|
// +----------+----------+--------------+-----------+
// DW3| CONTROL
// +----------+----------+--------------+-----------+
// DW4| RESERVED | RESERVED |
// +----------+----------+--------------+-----------+
CmdSlotNum->cfis.DW0.B0FisType=0x27;
CmdSlotNum->cfis.DW0.BYTE1=myCmdFis.cfisByte1;
field is correctly set or cleared.
CmdSlotNum->cfis.DW0.B2Cmd=myCmdFis.cfisCmd;
CmdSlotNum->cfis.DW0.B3Feature=myCmdFis.cfisFeature;
CmdSlotNum->cfis.DW1.B0LbaLow=myCmdFis.cfisDw1SecNumLbaLow;
CmdSlotNum->cfis.DW1.B1LbaMid=myCmdFis.cfisDw1CylLowLbaMid;
CmdSlotNum->cfis.DW1.B2LbaHigh=myCmdFis.cfisDw1CylHighLbahigh;
CmdSlotNum->cfis.DW1.B3Device=myCmdFis.cfisDw1Dev;
Addressing is indicated here.
CmdSlotNum->cfis.DW2.B0LbaLowExp=myCmdFis.cfisDw2SecNumLbaLowExp;
CmdSlotNum->cfis.DW2.B1LbaMidExp=myCmdFis.cfisDw2CylLowLbaMidExp;
CmdSlotNum->cfis.DW2.B2LbaHighExp=myCmdFis.cfisDw2CylHighLbahighExp; //0x0;
CmdSlotNum->cfis.DW2.B3FeatureExp=myCmdFis.cfisDw2FeatureExp;
CmdSlotNum->cfis.DW3.B0SecCnt=myCmdFis.cfisDw3SecCnt;
CmdSlotNum->cfis.DW3.B1SecCntExp=myCmdFis.cfisDw3SecCntExp;
CmdSlotNum->cfis.DW3.B2Rsv=0x0;
CmdSlotNum->cfis.DW3.B3Control=myCmdFis.cfisDw3Ctrl;
CmdSlotNum->cfis.DW4.DWResv=0x0;
}
char startCmdListProcessing(void) {
// Make sure that a device is present and HBA has established communications.
while ((sataRegs->P0SSTS & AHCI_PxSCTL_PxSSTS_DET) !=0x3);
// Clear P0SERR.DIAG.X (RWC bit field) so that the P0TFD is updated by HBA.
// Make sure it is cleared.
sataRegs->P0SERR |= 0x04000000;
// Make sure the Command List is not Running.
if (sataRegs->P0CMD & AHCI_PxCMD_CR)
return(1);
// Task file regs and look for Device ready status.
while ((sataRegs->P0TFD & AHCI_PxTFD_STS_BSY_DRQ_ERR) != 0);
// Make sure the the Receive FIS DMA is running.
if ((sataRegs->P0CMD & (AHCI_PxCMD_FRE | AHCI_PxCMD_FRE)) !=
return(1);
// Enable the Cmd List DMA Engine.
sataRegs->P0CMD |= AHCI_PxCMD_ST;
// Wait here a bit until the Command List DMA Engine has started to run
1586
Serial ATA (SATA) Controller
Preliminary
| c r r r port |FISTYPE 27h|
| LBA HIGH | LBA MID
LBAMIDexp
| RESERVED | SEC CNTexp
RESERVED
(AHCI_PxCMD_FRE | AHCI_PxCMD_FRE))
© 2011, Texas Instruments Incorporated
| LBA LOW |
| LBALOWexp |
| SEC CNT |
| RESERVED |
//Make Sure 48-Bit or 28-Bit
www.ti.com
//Make Sure the 'C' bit
//0x0;
//0x0;
//0x0;
//0x0;
SPRUGX9 – 15 April 2011
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