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within the submit queues. In other words, this memory needs not to be managed by the user software
and firmware responsibility lies only for allocation/reserving a chunk of memory for the use of the queue
manager. The allocated memory can be a single block of memory that is contiguous or two blocks of
memory that are not contiguous. These two blocks of memory are referred to as a Linking RAM
Regions and should not be confused with memory regions that are used to store descriptors. That is,
the use of the term region should be used in the context of its use.
To accomplish the linking of submitted descriptors, the queue manager will first resolve the 32-bit
descriptor pointer into a 16-bit index which is used for linking and queue pointer purposes. Once the
physical index information is determined, the queue manager will link that descriptor onto the descriptor
chain that is maintained for that logical queue by writing the linking information out to a linking RAM
which is external to the queue manager. The queue manager will also update the queue tail pointer
appropriately. Since logical queues within the queue manager are maintained using linked lists, queues
cannot become full and no check for fullness is required before queuing a packet descriptor.
The actual physical size of the Linking RAM region(s) to be allocated depends on the total number of
descriptors defined within all memory regions. A minimum of four bytes of memory needs to be
allocated for each Descriptor defined within all 16 memory regions.
The queue manager has the capability of managing up to 16 memory regions. These memory regions
are used to store descriptors of variable sizes. The total number of descriptors that can be managed by
the queue manager should not exceed 64K. Each memory region has descriptors of one configurable
size, that is, descriptors with different sizes cannot be housed within a single memory region. These
64K descriptors are referenced internally in the queue manager by a 16-bit quantity index.
The information about the Linking RAM regions and the size that are allocated is communicated to the
CPPI DMA via three registers dedicated for this purpose. Two of the three registers are used to store
the 32-bit aligned start addresses of the Linking RAM regions. The remaining one register is used to
store the size of the first Linking RAM. The linking RAM size value stored here is the number of
descriptors that is to be managed by the queue manager within that region not the physical size of the
buffer, which is four times the number of descriptors.
Note that application is not required to use both linking RAM regions, if the size of the Linking RAM for
the first region is large enough to accommodate all descriptors defined. No linking RAM size register for
linking RAM region 2 exists. The size of the second linking RAM, when used, is indirectly computed
from the total number of descriptors defined less the number of descriptors managed by the first linking
RAM
Figure 20-15
displays the relationship between several memory regions and linking RAM.
Figure 20-15. Relationship Between Memory Regions and Linking RAM
Memory Region 0
Base Address
Memory Region 1
Base Address
Memory Region 2
Base Address
Memory Region N
Base Address
SPRUGX9 – 15 April 2011
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Preliminary
Communications Port Programming Interface (CPPI) 4.1 DMA
Region 0
128 x 32
Bytes
Region 1
32 x 64
Bytes
Region 2
64 x 32
Bytes
Region N
64 x 32
Bytes
© 2011, Texas Instruments Incorporated
0
Index w
64
Entries
Index x
128
Entries
Linking RAM
Region 0
Index y
64 Entries
Index z
32
Entries
Linking RAM
Region 1
65535
Universal Serial Bus (USB)
1807
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