Example Of Spi Slave With One Master And Multiple Slave Devices On Channel - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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Figure 12-22. Example of SPI Slave with One Master and Multiple Slave Devices on Channel 0
Device
12.2.4.2 Interrupt Events in Slave Mode
The interrupt events related to the transmitter register state are TX_empty and TX_underflow. The
interrupt events related to the receiver register state are RX_full and RX_overflow.
12.2.4.2.1 TX_EMPTY
The event TX_empty is activated when the channel is enabled and its transmitter register becomes
empty. Enabling channel automatically raises this event. When FIFO buffer is enabled
(MCSPI_CH(I)CONF[FFEW] set to 1), the TX_empty is asserted as soon as there is enough space in
buffer to write a number of byte defined by MCSPI_XFERLEVEL[AEL].
Transmitter register must be load to remove source of interrupt and TX_empty interrupt status bit must
be cleared for interrupt line de-assertion (if event enable as interrupt source).
When FIFO is enabled, no new TX_empty event will be asserted as soon as Local Host has not
performed the number of write into transmitter register defined by MCSPI_XFERLEVEL[AEL]. It is the
responsibility of Local Host to perform the right number of writes.
SPRUGX9 – 15 April 2011
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Preliminary
McSPI
module m
spim_clk
spim_simo
spim_somi
spim_cs0
Generic
SPI slave
SCLK
device
SIMO
SOMI
© 2011, Texas Instruments Incorporated
SCLK
SIMO
SOMI
CS
SCLK
SIMO
SOMI
CS
CS
SCLK
SIMO
SOMI
CS
Multichannel Serial Port Interface (McSPI)
Architecture
Generic
SPI master
device
Generic
SPI slave
device
Generic
SPI slave
device
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