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Reset Management
Once the PRCM sees that this MPU_PWRN_RSTDONE signal is asserted HIGH, PRCM de-asserts the
MPU_RST signal and then the MPU starts booting.
14.5.6 MPU Subsystem Warm Sequence
During the warm reset of MPU, the PRCM asserts the MPU_RST signal only and power on reset signal
is not asserted.
The MPU_RST is kept asserted for minimum 32 MPU clock cycles, that is, SYS_CLK in this case since
during warm the reset of MPU.
14.5.7 C674x DSP Power-On Reset Sequence
The assumptions about POR de-assertion are:
•
The MPU software sets the CM_ACTIVE_GEM_CLKCTRL [1:0] MODULEMODE bit field to
enabled.
•
The MPU software sets the CM_ACTIVE_GEM_CLKSTCTRL [1:0] CLKTRCTRL bit field to
SW_WKUP.
•
The PRCM is providing the clocks to C674x DSP.
The POR sequence is:
•
The PRCM module releases GEM_POR when the reset manager counter (PRM_RSTTIME[14:10]
RSTTIME2) reaches its limit.
•
The MPU software clears the RM_ACTIVE_RSTCTRL[1] GEM_SW_RST bit in the PRCM module
register to release the DSP, MMU, and CACHE interface from reset.
•
Once the reset manager counter (PRM_RSTTIME[14:10] RSTTIME2) expires, the PRCM module
releases the GEM_GRST signal.
•
On deassertion of the GEM_GRST signal, the C674x subsystem starts the initialization sequence.
During the initialization sequence all the internal registers inside the C674x subsystem are properly
reset and the reset for the DSP, MMU, and CACHE interface completes.
•
The MPU software must configure the MMU once the MMU is out of reset. After the MMU is
configured, the MPU software clears the RM_ACTIVE_RSTCTRL[0] GEM_LRST bit in the PRCM
module register.
The PRCM module releases GEM_LRST, which causes the DSP to start booting.
14.5.8 C674x DSP Warm Reset Sequence
The assumptions about WARM reset de-assertion are:
•
The DSP is in IDLE state
The sequence is:
1. The MPU software sets the RM_ACTIVE_RSTCTRL[1] GEM_SW_RST and
RM_ACTIVE_RSTCTRL[0] GEM_LRST bits.
2. The PRCM module asserts the GEM_GRST and GEM_LRST reset signals.GEM_POR remains
deasserted in this case.
3. The MPU software re-enables the C674x DSP Clocks and clears the RM_ACTIVE_RSTCTRL[1]
GEM_SW_RST bit in the PRCM module register to reset the DSP, MMU, and CACHE interface.
The DSP subsystem starts the partial initialization sequence for the warm reset.
4. The MPU software clears the RM_ACTIVE_RSTCTRL[0] GEM_LRST bit in the PRCM module
register.
5. The PRCM module releases GEM_LRST, which causes the DSP to start booting.
1420
Power, Reset, and Clock Management (PRCM) Module
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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