Intcps_Mirn Register; Intcps_Mir_Clearn Register; Intcps_Mir_Setn Register; Intcps_Mirn Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers
8.4.13 INTCPS_MIR0-3 Registers
This register contains the interrupt mask.
31
LEGEND: R = Read only; -n = value after reset
Bit Field
31-0 MR[n]
8.4.14 INTCPS_MIR_CLEAR0-3 Registers
This register is used to clear the interrupt mask bits.
31
LEGEND: W = Write only; -n = value after reset
Bit Field
31-0 MIRCLEAR[n]
8.4.15 INTCPS_MIR_SET0-3 Registers
This register is used to set the interrupt mask bits.
31
LEGEND: W = Write only; -n = value after reset
Bit Field
31-0 MIRSET[n]
924
Interrupt Controller
Preliminary
Figure 8-18. INTCPS_MIRn Register
R/W-FFFF FFFFh
Table 8-16. INTCPS_MIRn Register Field Descriptions
Value Description
Interrupt mask
0 Interrupt is unmasked.
1 Interrupt is masked.
Figure 8-19. INTCPS_MIR_CLEARn Register
MIRCLEAR[n]
Table 8-17. INTCPS_MIR_CLEARn Register Field Descriptions
Value Description
Clear the interrupt mask [n] bits. Read returns 0
W0 No effect.
W1 Clears the MIR mask bit [n] to 0.
Figure 8-20. INTCPS_MIR_SETn Register
MIRSET[n]
Table 8-18. INTCPS_MIR_SETn Register Field Descriptions
Value Description
Mask the interrupt [n] bits. Read returns 0.
W0 No effect.
W1 Set the MIR mask [n] bit to 1
© 2011, Texas Instruments Incorporated
MR[n]
W-0
W-0
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0
0
0
SPRUGX9 – 15 April 2011
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