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Table 20-6. Isochronous OUT Error Handling: Peripheral Mode (continued)
No. Packet(s) Expected
3
20.3.2 USB Controller Host Mode Operation
The USB controller assumes the role of a host when the USB Mode Register[iddig=bit8] is cleared to 0
by the firmware prior to the controller goes into session. When the USB controller go into session,
application/firmware sets the DEVCTL[SESSION] bit to 1, it will assume the role of a host.
•
Entry into Suspend mode. When operating as a host, the USB controller can be prompted to go into
Suspend mode by setting the SUSPENDM bit in the POWER register. When this bit is set, the
controller will complete the current transaction then stop the transaction scheduler and frame
counter. No further transactions will be started and no SOF packets will be generated.
If the ENSUSPM bit (bit 0 of POWER register) is set, the UTMI+ PHY will go into low-power mode
when the controller goes into suspend mode.
•
Sending Resume Signaling. When the application requires the controller to leave suspend mode, it
needs to clear the SUSPENDM bit in the POWER register, set the RESUME bit and leave it set for
20ms. While the RESUME bit is high, the controller will generate Resume signaling on the bus. After
20 ms, the CPU should clear the RESUME bit, at which point the frame counter and transaction
scheduler will be started.
•
Responding to Remote Wake-up. If Resume signaling is detected from the target while the controller
is in suspend mode, the UTMI+ PHY will be brought out of low-power mode and UTMI clock is
restarted. The controller will then exit suspend mode and automatically set the RESUME bit in the
POWER register (bit 2) to '1' to take over generating the Resume signaling from the target. If the
resume interrupt is enabled, an interrupt will be generated.
•
Reset Signaling. If the RESET bit in the POWER register (bit 3) is set while the controller is in Host
mode, it will generate Reset signaling on the bus. If the HSENAB bit in the POWER register (bit 5)
was set, it will also try to negotiate for high-speed operation. The software should keep the RESET
bit set for at least 20 ms to ensure correct resetting of the target device. After the software has
cleared the bit, the controller will start its frame counter and transaction scheduler. Whether
high-speed operation is selected will be indicated by HSMODE bit of POWER register (bit 4).
SPRUGX9 – 15 April 2011
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Preliminary
Data Packet(s) Received
DATA0
DATA1
DATA2
MDATA
MDATA DATA0
MDATA DATA1
MDATA DATA2
MDATA MDATA
MDATA MDATA DATA0
MDATA MDATA DATA1
MDATA MDATA DATA2
MDATA MDATA MDATA
© 2011, Texas Instruments Incorporated
Protocol Description(s)
Response
OK
INCOMPRX Set
INCOMPRX Set
INCOMPRX Set
PID Error set
OK
INCOMPRX Set
INCOMPRX Set
PID Error set
PID Error set
OK
PID Error set
1777
Universal Serial Bus (USB)
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