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Protocol Description(s)
20.3.2.1.2 Data Phase (IN Data Phase) of a Control Transaction: Host Mode
For the IN Data Phase of a control transaction
needs to
1. Set REQPKT bit of HOST_CSR0 (bit 5)
2. Wait while the controller sends the IN token and receives the required data back.
3. When the controller generates the Endpoint 0 interrupt, read HOST_CSR0 to establish whether the
RXSTALL bit (bit 2), the ERROR bit (bit 4), the NAK_TIMEOUT bit (bit 7) or RXPKTRDY bit (bit 0)
has been set.
If RXSTALL is set, it indicates that the target has issued a STALL response.
If ERROR is set, it means that the controller has tried to send the required IN token three times
without getting any response. If NAK_TIMEOUT bit is set, it means that the controller has received a
NAK response to each attempt to send the IN token, for longer than the time set in
HOST_NAKLIMIT0. The controller can then be directed either to continue trying this transaction
(until it times out again) by clearing the NAK_TIMEOUT bit or to abort the transaction by clearing
REQPKT before clearing the NAK_TIMEOUT bit
4. If RXPKTRDY has been set, the software should read the data from the Endpoint 0 FIFO, then clear
RXPKTRDY.
5. If further data is expected, the software should repeat Steps 1-4.
When all the data has been successfully received, the CPU should proceed to the OUT Status Phase
of the Control Transaction.
1780
Universal Serial Bus (USB)
Preliminary
(Figure
20-8), the software driving the USB host device
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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