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Architecture
A break condition is asserted as long as LCR[6] is set to 1. The above functionality (timeout counter
and break condition) only applies to the UART Modem operation and does not extend to the IrDA/CIR
modes of operation.
NOTE: A break condition is asserted irrespective of CTS state when auto-CTS is programmed.
19.2.3.4 UART Configuration Example
This section proposes outlines the programming stages to operate one UART module with FIFO,
interrupt and no DMA capabilities. This is a three-step procedure that ensures quick start of these
modules (obviously it does not cover every UART module feature). The first stage covers SW reset of
the module (interrupts, status and controls); the second stage deals with FIFO configuration and
enable. Finally, last stage deals with the baud rate data and stop configuration. The procedure below is
programming language agnostic.
19.2.3.4.1 UART Software Reset
Goal: To clear IER and MCR registers: remove UART breaks (LCR[6] = 0) and put module in reset
(MDR1[2:0] = 7h).
Procedure: To write into both the IER and MCR register, EFR[4] must first be set to 1. To be able to
access the EFR register, BFh must first be written to LCR register. Hence LCR = BFh; first write to the
LCR register EFR[4] = 1. When LCR = BFh, enable the enhanced feature register LCR[7] = 0. Here,
access to IER and MCR is allowed. IER = 0; disable interrupt MCR = 0. Force control signals inactive
LCR[6] = 0. Here, UART breaks are removed MDR1 = 7h. Here, UART is in reset or disabled.
Alternatively, the SYSC[1] can be set to 1 to start a hardware reset from the generic synchronous reset
module. The reset progress can be monitored via the SYSS[0]. Once complete the above sequence
should ensure the UART is in the equivalent disabled mode with reference to MDR1[2:0].
19.2.3.4.2 UART FIFO Configuration
Goal: To set trigger level for halt/restore (TCR register), set trigger level for transmit/receive (TLR
register), and configure FIFO (FCR register).
Procedure: To write into both the TLR and TCR registers, EFR[4] must be set to 1 and MCR[6] to 1. To
write into FCR, EFR[4] must be set to 1. Note that EFR[4] = 1 has already been done in the previous
section, hence a write to MCR[6] is necessary. MCR[6] = 1; set TCR, TLR, and FCR to the desired
value. Here, accesses to TCR, TLR, and FCR must be disabled to avoid any further undesired writes to
these registers. Hence, LCR = BFh, provides access to EFR, EFR[4] = 0; LCR[7] = 0; MCR[6] = 0.
19.2.3.4.3 Baud Rate Data and Stop Configuration
Goal: To configure UART data and stop (LCR register). baud rate (DLH and DLL registers), and enable
UART operation. In case interrupt capability is added, configuration must be added right before UART
enable.
Procedure: Set LCR to desired value; LCR[7] to 1, gives access to DLH and DLL registers. Set DLH
and DLL; LCR[7] = 0, removes access to DLH and DLL registers. Set IER to desired value. Set
interrupts MDR1[2:0] = 0; enables UART without autobauding.
The UART module is operational.
1686
UART/IrDA/CIR Module
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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