Table of Contents
Advertisement
www.ti.com
9.2.4 Interrupt Requests
Several internal module events can generate an interrupt. Each interrupt has a status bit, an interrupt
enable bit, and a signal status enable:
•
The status of each type of interrupt is automatically updated in the SD_STAT register; it indicates
which service is required.
•
The interrupt status enable bits of the SD_IE register enable/disable the automatic update of the
SD_STAT register on an event-by-event basis.
•
The interrupt signal enable bits of the SD_ISE register enable/disable the transmission of an
interrupt request on the interrupt line IRQ (from the SD/SDIOi host controller to the MPU subsystem
interrupt controller) on an event-by-event basis.
If an interrupt status is disabled in the SD_IE register, then the corresponding interrupt request is not
transmitted, and the value of the corresponding interrupt signal enable in the SD_ISE register is
ignored.
When an interrupt event occurs, the corresponding status bit is automatically set to 1 (the SD/SDIO
host controller updates the status bit) in the SD_STAT register. If later a mask is applied on the
interrupt in the SD_ISE register, the interrupt request is deactivated.
When the interrupt source has not been serviced, if the interrupt status is cleared in the SD_STAT
register and the corresponding mask is removed from the SD_ISE register, the interrupt status is not
asserted again in the SD_STAT register and the SD/SDIOi host controller does not transmit an interrupt
request.
If the buffer write ready interrupt (BWR) or the buffer read ready only
interrupt (BRR) are not serviced and are cleared in the SD_STAT register,
and the corresponding mask is removed, then the SD/SDIOi host controller
will wait for the service of the interrupt without updating the status SD_STAT
or transmitting an interrupt request.
Table 9-5
lists the event flags, and their mask, that can cause module interrupts.
Event Flag
Event Mask
SD_STAT[29] BADA
SD_IE[29]
BADA_ENABLE
SD_STAT[28] CERR
SD_IE[28]
CERR_ENABLE
SD_STAT[25] ADMAE
SD_IE[25]
ADMAE_ENABLE
SD_STAT[24] ACE
SD_IE[24]
ACE_ENABLE
SD_STAT[22] DEB
SD_IE[22]
DEB_ENABLE
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Preliminary
CAUTION
Table 9-5. Events
Map To
Description
IRQ
Bad Access to Data space. This bit is set automatically to indicate a bad
access to buffer when not allowed. This bit is set during a read access to
the data register (SD_DATA) while buffer reads are not allowed
(SD_PSTATE[11] BRE=0). This bit is set during a write access to the data
register (SD_DATA) while buffer writes are not allowed (SD_STATE[10]
BWE=0)
IRQ
Card Error. This bit is set automatically when there is at least one error in a
response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type
E(error) in status field in the response can set a card status error. An error
bit in the response is flagged only if corresponding bit in card status
response errros SD_CSRE is set. There is not card detection for auto
CMD12 command.
IRQ
AMDA error. This bit is set when the host controller detects errors during
ADMA based data transfer. The stat of the ADMA at an error occurrence is
saved in the ADMA Error Status Register. In addition, the host controller
generates this interrupt when it detects invalid descriptor data (Valid=0) at
teh ST_FDS state.
IRQ
Auto CMD12 error. This bit is set automatically when one of the bits in Auto
CMD12 Error status register has changed from 0 to 1
IRQ
Data End Bit error. This bit is set automatically when detecting a 0 at the
end bit position of read data on DAT line or at the end position of the CRC
status in write mode.
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
© 2011, Texas Instruments Incorporated
Architecture
937
Advertisement
Table of Contents
