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Protocol Description(s)
20.3.2.1 Control Transactions: Host Mode
Host control transactions are conducted through Endpoint 0 and the software is required to handle all
the Standard Device Requests that may be sent or received via Endpoint 0 (as described in Universal
Serial Bus Specification, Revision 2.0). Endpoint 0 can only be serviced via CPU and DMA mode can
not be used.
There are three categories of Standard Device Requests to be handled: Zero Data Requests (in which
all the information is included in the command); Write Requests (in which the command will be followed
by additional data); and Read Requests (in which the device is required to send data back to the host).
1. Zero Data Requests comprise a SETUP command followed by an IN Status Phase.
2. Write Requests comprise a SETUP command, followed by an OUT Data Phase which is in turn
followed by an IN Status Phase.
3. Read Requests comprise a SETUP command, followed by an IN Data Phase which is in turn
followed by an OUT Status Phase.
A timeout may be set to limit the length of time for which the host controller will retry a transaction
which is continually NAKed by the target. This limit can be between 2 and 2 15 frames/microframes and
is set through the NAKLIMIT0 register.
The following sections describe the actions that the CPU needs to take in issuing these different types
of request through looking at the steps to take in the different phases of a control transaction.
Note: Before initiating any transactions as a Host, the FADDR register needs to be set to address the
peripheral device. When the device is first connected, FADDR should be set to zero. After a
SET_ADDRESS command is issued, FADDR should be set the target's new address.
20.3.2.1.1 Setup Phase of Control Transaction: Host Mode
For the SETUP Phase of a control transaction
needs to:
1. Load the 8 bytes of the required Device request command into the Endpoint 0 FIFO
2. Set SETUPPKT and TXPKTRDY (bits 3 and 1 of HOST_CSR0, respectively).
NOTE: These bits must be set together.
The controller then proceeds to send a SETUP token followed by the 8-byte command/request to
Endpoint 0 of the addressed device, retrying as necessary. Note: On errors, the controller retries the
transaction three times.
3. At the end of the attempt to send the 8-byte request data, the controller will generate an Endpoint 0
interrupt. The software should then read HOST_CSR0 to establish whether the RXSTALL bit (bit 2),
the ERROR bit (bit 4) or the NAK_TIMEOUT bit (bit 7) has been set.
If RXSTALL is set, it indicates that the target did not accept the command (for example, because it
is not supported by the target device) and so has issued a STALL response. If ERROR is set, it
means that the controller has tried to send the SETUP Packet and the following data packet three
times without getting any response.
If NAK_TIMEOUT is set, it means that the controller has received a NAK response to each attempt
to send the SETUP packet, for longer than the time set in HOST_NAKLIMIT0. The controller can
then be directed either to continue trying this transaction (until it times out again) by clearing the
NAK_TIMEOUT bit or to abort the transaction by flushing the FIFO before clearing the
NAK_TIMEOUT bit.
4. If none of RXSTALL, ERROR or NAK_TIMEOUT is set, the SETUP Phase has been correctly
ACKed and the software should proceed to the following IN Data Phase, OUT Data Phase or IN
Status Phase specified for the particular Standard Device Request.
1778
Universal Serial Bus (USB)
Preliminary
(Figure
20-7), the software driving the USB host device
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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