Prefetch_Base Register; Prefetch_Limit Register; Iospace Register; Prefetch_Base Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

13.4.7.8 PREFETCH_BASE Register

The prefetchable memory base upper 32 bits register (PREFETCH_BASE) is described in the figure
and table below.
31
LEGEND: R/W = Read/Write; -n = value after reset
Bit Field
31-0 Base Address

13.4.7.9 PREFETCH_LIMIT Register

The prefetchable limit upper 32 bits register (PREFETCH_LIMIT) is described in the figure and table
below.
31
LEGEND: R/W = Read/Write; -n = value after reset
Bit Field
31-0 Limit Address

13.4.7.10 IOSPACE Register

The IO base and limit upper 16 bits register (IOSPACE) is described in the figure and table below.
31
15
LEGEND: R/W = Read/Write; -n = value after reset
Bit Field
31-16 IOBASE
15-0 IOLIMIT
1360
Peripheral Component Interconnect Express (PCIe)
Preliminary
Figure 13-99. PREFETCH_BASE Register
Base Address
Table 13-105. PREFETCH_BASE Field Descriptions
Value Description
0-FFFF FFFFh Upper 32 bits of base address of prefetchable memory space. Used when 64 bit
addressing is enabled.
Figure 13-100. PREFETCH_LIMIT Register
Base Address
Table 13-106. PREFETCH_LIMIT Register Field Descriptions
Value Description
0-FFFF FFFFh Upper 32 bits of Limit Address of Prefetchable Memory Space. Used with 64 bit
prefetchable memory addressing only.
Figure 13-101. IOSPACE Register
IOBASE
IOLIMIT
Table 13-107. IOSPACE Register Field Descriptions
Value Description
0-FFFFh Upper 16 bits of IO Base
0-FFFFh Upper 16 bits of IO Limit
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SPRUGX9 – 15 April 2011
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