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Architecture
10.2.11 Interrupts
10.2.11.1 Interrupt Multiplexing
The processor includes an interrupt controller (INTC) to manage CPU interrupts. The INTC maps the
device events to 12 CPU interrupts. The McASP generates 4 interrupts to the processor.
The event inputs can be routed to 12 maskable interrupts to the CPU (INT[15:4]). The INTC interrupt
selector allows the McASP system events to be routed to any of the 12 CPU interrupt inputs.
Furthermore, the INTC provides status flags and allows the combination of events, as shown in
Figure
10-33. You must properly configure the INTC by enabling, masking, and routing the McASP
system events to the desired CPU interrupts.
(from McASP)
10.2.11.2 Transmit Data Ready Interrupt
The transmit data ready interrupt (XDATA) is generated if XDATA is 1 in the XSTAT register and
XDATA is also enabled in XINTCTL.
XSTAT register.
A transmit start of frame interrupt (XSTAFRM) is triggered by the recognition of transmit frame sync. A
transmit last slot interrupt (XLAST) is a qualified version of the data ready interrupt (XDATA). It has the
same behavior as the data ready interrupt, but is further qualified by having the data requested
belonging to the last slot (the slot that just ended was next-to-last TDM slot, current slot is last slot).
10.2.11.3 Receive Data Ready Interrupt
The receive data ready interrupt (RDATA) is generated if RDATA is 1 in the RSTAT register and
RDATA is also enabled in RINTCTL.
RSTAT register.
A receiver start of frame interrupt (RSTAFRM) is triggered by the recognition of a receiver frame sync.
A receiver last slot interrupt (RLAST) is a qualified version of the data ready interrupt (RDATA). It has
the same behavior as the data ready interrupt, but is further qualified by having the data in the buffer
come from the last TDM time slot (the slot that just ended was last TDM slot).
10.2.11.4 Error Interrupts
Upon detection, the following error conditions generate interrupt flags:
•
In the receive status register (RSTAT):
– Receiver overrun (ROVRN).
– Unexpected receive frame sync (RSYNCERR).
– Receive clock failure (RCKFAIL).
– Receive DMA error (RDMAERR).
1062
Multichannel Audio Serial Port (McASP)
Preliminary
Figure 10-33. Interrupt Multiplexing
Event
flags
EVT[59:60]
Section 10.2.8.1.1
Section 10.2.8.1.2
© 2011, Texas Instruments Incorporated
Event
combiner
EVT[3:0]
INT[15:4]
Interrupt
(to CPU)
selector
provides details on when XDATA is set in the
provides details on when RDATA is set in the
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SPRUGX9 – 15 April 2011
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