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10.2.8.4 Error Handling and Management
To support the design of a robust audio system, the McASP includes error-checking capability for the
serial protocol, data underrun, and data overrun. In addition, the McASP includes a timer that
continually measures the high-frequency master clock every 32 AHCLKX/AHCLKR clock cycles. The
timer value can be read to get a measurement of the clock frequency and has a minimum and
maximum range setting that can set an error flag if the master clock goes out of a specified range.
Upon the detection of any one or more errors (software selectable), or the assertion of the AMUTEIN
input pin, the AMUTE output pin may be asserted to a high or low level to immediately mute the audio
output. In addition, an interrupt may be generated if desired, based on any one or more of the error
sources.
10.2.8.4.1 Unexpected Frame Sync Error
An unexpected frame sync occurs when:
•
In burst mode, when the next active edge of the frame sync occurs early such that the current slot
will not be completed by the time the next slot is scheduled to begin.
•
In TDM mode, a further constraint is that the frame sync must occur exactly during the correct bit
clock (not a cycle earlier or later) and only before slot 0. An unexpected frame sync occurs if this
condition is not met.
When an unexpected frame sync occurs, there are two possible actions depending upon when the
unexpected frame sync occurs:
1. Early: An early unexpected frame sync occurs when the McASP is in the process of completing the
current frame and a new frame sync is detected (not including overlap that occurs due to a 1 or 2 bit
frame sync delay). When an early unexpected frame sync occurs:
•
Error interrupt flag is set (XSYNCERR, if an unexpected transmit frame sync occurs;
RSYNCERR, if an unexpected receive frame sync occurs).
•
Current frame is not resynchronized. The number of bits in the current frame is completed. The
next frame sync, which occurs after the current frame is completed, will be resynchronized.
2. Late: A late unexpected frame sync occurs when there is a gap or delay between the last bit of the
previous frame and the first bit of the next frame. When a late unexpected frame sync occurs (as
soon as the gap is detected):
•
Error interrupt flag is set (XSYNCERR, if an unexpected transmit frame sync occurs;
RSYNCERR, if an unexpected receive frame sync occurs).
•
Resynchronization occurs upon the arrival of the next frame sync.
Late frame sync is detected the same way in both burst mode and TDM mode; however, in burst mode,
late frame sync is not meaningful and its interrupt enable should not be set.
10.2.8.4.2 Buffer Underrun Error - Transmitter
A buffer underrun can only occur for serializers programmed to be transmitters. A buffer underrun
occurs when the serializer is instructed by the transmit state machine to transfer data from XRBUF[n] to
XRSR[n], but XRBUF[n] has not yet been written with new data since the last time the transfer
occurred. When this occurs, the transmit state machine sets the XUNDRN flag.
An underrun is checked only once per time slot. The XUNDRN flag is set when an underrun condition
occurs. Once set, the XUNDRN flag remains set until the processor explicitly writes a 1 to the XUNDRN
bit to clear the XUNDRN bit.
In DIT mode, a pair of BMC zeros is shifted out when an underrun occurs (four bit times at 128 × fs). By
shifting out a pair of zeros, a clock may be recovered on the receiver. To recover, reset the McASP and
start again with the proper initialization.
In TDM mode, during an underrun case, a long stream of zeros are shifted out causing the DACs to
mute. To recover, reset the McASP and start again with the proper initialization.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Multichannel Audio Serial Port (McASP)
Architecture
1051
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