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TMS320C6A816 Series
Texas Instruments TMS320C6A816 Series Manuals
Manuals and User Guides for Texas Instruments TMS320C6A816 Series. We have
1
Texas Instruments TMS320C6A816 Series manual available for free PDF download: Technical Reference Manual
Texas Instruments TMS320C6A816 Series Technical Reference Manual (2034 pages)
C6-Integra DSP+ARM Processors
Brand:
Texas Instruments
| Category:
Control Unit
| Size: 11.84 MB
Table of Contents
Table of Contents
3
Preface
91
Chip Level Resources
93
Introduction
94
MPU Subsystem
94
1.2.2 Features
95
Microprocessor Unit (MPU) Subsystem
95
1.2.3 MPU Subsystem Integration
96
Microprocessor Unit (MPU) Subsystem Signal Interface
97
1.2.4 MPU Subsystem Clock and Reset Distribution
98
MPU Subsystem Clocking Scheme
98
MPU Subsystem Clock Frequencies
99
MPU Subsystem Clock Input Signals
99
Reset Scheme of the MPU Subsystem
100
1.2.5 ARM Subchip
101
ARM Core Supported Features
101
1.2.6 AXI2OCP and I2Async Bridges
102
Overview of the AXI2OCP and the L3 Bridges
102
Read Channel AXI ID to OCP Tag Mappings
103
Write Channel AXI ID to OCP Tag Mappings
103
1.2.7 Interrupt Controller
104
1.2.8 Power Management
104
MPU Subsystem Power Domain Overview
105
Overview of the MPU Subsystem Power Domain
105
MPU Power States
106
MPU Subsystem Operation Power Modes
106
1.2.9 Host ARM Address Map
107
1.2.10 ARM Programming Model
107
Address Map of the MPU Subsystem
107
C674X DSP Subsystem
109
1.3.1 Introduction
109
1.3.2 Key Features
110
Tms320C674X Megamodule Block Diagram
110
1.3.3 DSP Subsystem Functional Description
111
1.3.4 Tms320C674X Megamodule
112
DSP Subsystem Block Diagram
112
Clocks
112
Tms320C674X Megamodule Block Diagram
113
DSP Megamodule INTC Block Diagram
115
Advanced Event Triggering (AET)
116
System MMU
117
1.4.1 MMU Overview
117
1.4.2 MMU Intergration
117
Typical MMU Intergration
117
1.4.3 MMU Functional Description
118
MMU Block Diagram
118
MMU Address Translation Process
119
Translation Hierarchy
120
First-Level Descriptor Address Calculation
120
Detailed First-Level Descriptor Address Calculation
121
First-Level Descriptor Format
121
Section Translation Summary
122
Supersection Translation Summary
123
Two-Level Translation
124
Small Page Translation Summary
125
Second-Level Descriptor Format
125
Large Page Translation Summary
126
TLB-Entry Lock Mechanism
127
TLB-Entry Structure
128
Mmu_Sysconfig
128
MMU Local Power Management Features
129
Error Handling
129
1.4.4 MMU Low-Level Programming Models
130
MMU Global Initialization
130
Mmu_Ld_Tlb
130
Mmu_Sysstatus
131
Mmu_Irqenable
131
Mmu_Cam
131
Mmu_Ram
131
Configure a TLB Entry
131
MMU Writing TLB Entries Statically
131
Protecting TLB Entries
131
Mmu_Gflush
132
Mmu_Flush_Entry
132
Deleting TLB Entries
132
Read TLB Entries
132
1.4.5 MMU Registers
133
MMU Instance Summary
133
MMU_REVISION Field Descriptions
133
MMU_SYSCONFIG Field Descriptions
134
MMU_SYSSTATUS Field Descriptions
135
MMU_IRQSTATUS Field Descriptions
136
MMU_IRQENABLE Field Descriptions
137
Mmu_Walking_St
138
Mmu_Cntl
138
Mmu_Fault_Ad
139
Mmu_Ttb
139
Mmu_Lock
139
MMU_LD_TLB Field Descriptions
140
MMU_CAM Field Descriptions
140
MMU_RAM Field Descriptions
141
MMU_GFLUSH Field Descriptions
141
Mmu_Read_Cam
142
MMU_FLUSH_ENTRY Field Descriptions
142
MMU_READ_CAM Field Descriptions
142
Mmu_Read_Ram
143
Mmu_Emu_Fault_Ad
144
Mmu_Fault_Pc
144
SGX530 Graphics Subsystem
145
1.5.1 SGX Overview
145
Graphics Accelerator Highlight
145
1.5.2 SGX Integration
148
SGX Subsystem Integration
148
Clock Descriptions
148
1.5.3 SGX Functional Description
150
SGX Block Diagram
150
1.5.4 SGX Registers
152
SGX Registers Mapping Summary
152
OCP Revision Register (OCP_REVISION) Field Descriptions
153
Hardware Implementation Information Register (OCP_HWINFO) Field Descriptions
153
System Configuration Register (OCP_SYSCONFIG) Field Descriptions
154
Raw IRQ 0 Status Register (OCP_IRQSTATUS_RAW_0) Field Descriptions
155
Raw IRQ 1 Status Register (OCP_IRQSTATUS_RAW_1) Field Descriptions
155
Raw IRQ 2 Status Register (OCP_IRQSTATUS_RAW_2) Field Descriptions
156
Interrupt 0 Status Event Register (OCP_IRQSTATUS_0) Field Descriptions
156
Interrupt 1 Status Event Register (OCP_IRQSTATUS_1) Field Descriptions
157
Interrupt 2 Status Event Register (OCP_IRQSTATUS_2) Field Descriptions
157
Enable Interrupt 0 Register (OCP_IRQENABLE_SET_0) Field Descriptions
158
Enable Interrupt 1 Register (OCP_IRQENABLE_SET_1) Field Descriptions
158
Enable Interrupt 2 Register (OCP_IRQENABLE_SET_2) Field Descriptions
159
Disable Interrupt 0 Register (OCP_IRQENABLE_CLR_0) Field Descriptions
159
Disable Interrupt 1 Register (OCP_IRQENABLE_CLR_1) Field Descriptions
160
Disable Interrupt 2 Register (OCP_IRQENABLE_CLR_2) Field Descriptions
160
Configure Memory Page Register (OCP_PAGE_CONFIG) Field Descriptions
161
Interrupt Events Register (OCP_INTERRUPT_EVENT)
162
Interrupt Events Register (OCP_INTERRUPT_EVENT) Field Descriptions
163
Configuration of Debug Modes Register (OCP_DEBUG_CONFIG) Field Descriptions
164
Debug Status Register (OCP_DEBUG_STATUS) Field Descriptions
165
HD Video Processing Subsystem (HDVPSS)
167
1.6.1 Features Supported
167
System Memory Map
170
Device Interrupts
171
1.8.1 Interrupt Requests to Cortex-A8 MPU INTC
171
Cortex-A8 MPU INTC Interrupt Mapping
171
1.8.2 Interrupt Requests to Media Controller INTC
174
Media Controller INTC Interrupt Mapping
174
1.8.3 Interrupt Requests to DSP INTC
176
DSP INTC Interrupt Mapping
176
EDMA and EDMA Events
179
1.9.1 Overview
179
1.9.2 EDMA Regions
179
1.9.3 Synchronization Events
179
EDMA Channel Synchronization Events
180
1.10 Device Clocking and Flying Adder PLL
182
1.10.1 Overview
182
Top Level Clock Architecture
182
Device Clock Inputs
183
System Clock Domains
183
Detailed Clock Architecture
185
Mailbox
185
1.10.2 I/O Domains
186
External Peripheral Clock Sources
186
1.10.3 Flying Adder PLL
187
Main PLL Structure
188
MAIN PLL Dividers
188
Main PLL Clocks
189
Example for Main PLL Frequencies
190
DDR PLL Structure
191
DDR PLL Dividers
191
DDR PLL Clocks
191
Example for DDR PLL Frequencies
192
Video PLL Structure
193
Video PLL Dividers
193
Video PLL Clocks
194
Example for Video PLL Frequencies
194
Audio PLL Structure
195
Audio PLL Dividers
195
Audio PLL Clocks
196
Example for Audio PLL Frequencies
196
1.10.4 Clock out
198
1.11 Bus Interconnect
199
1.11.1 Terminology
199
1.11.2 L3 Interconnect
199
L3 Interconnect Block Diagram
200
Device Mconnid Assignment
202
L3 Master/Slave Connectivity (Table 1 of 2)
203
L3 Master/Slave Connectivity (Table 2 of 2)
204
1.12 Inter-Processor Communication
205
1.12.1 Reset Requirements
205
1.12.2 Features
205
1.12.3 Overview and Strategy
206
IPC Overview Diagram
206
System Ipcs
207
1.12.4 IPC Component Configuration
208
Hardware Spinlock Configuration
208
1.13 Mailbox
209
1.13.1 Overview
209
1.13.2 System Mailbox Integration
209
1.13.3 Functional Description
210
Integration Attributes
210
Clocks and Resets
210
Hardware Requests
210
Mailbox Implementation
210
Mailbox Block Diagram
211
Local Power Management Features
212
Interrupt Events
212
1.13.4 Programming Guide
214
Global Initialization of Surrounding Modules for System Mailbox
214
Mailbox Global Initialization
215
Sending a Message (Polling Method)
215
Sending a Message (Interrupt Method)
215
Receiving a Message (Polling Method)
216
Receiving a Message (Interrupt Method)
216
Events Servicing in Sending Mode
216
Events Servicing in Receiving Mode
216
1.13.5 Mailbox Registers
217
Mailboxes
217
Mailbox Registers Mapping Summary
217
Revision Register (MAILBOX_REVISION)
218
System Configuration Register (MAILBOX_SYSCONFIG) Field Descriptions
218
Message Register (Mailbox_Message_M) Field Descriptions
219
FIFO Status Register (Mailbox_Fifostatus_M) Field Descriptions
219
Message Status Register (Mailbox_Msgstatus_M)
220
IRQ RAW Status Register (Mailbox_Irqstatus_Raw_U) Field Descriptions
221
IRQ RAW Status Register (Mailbox_Irqstatus_Raw_U)
222
IRQ Clear Status Register (Mailbox_Irqstatus_Clr_U) Field Descriptions
225
IRQ Clear Status Register (Mailbox_Irqstatus_Clr_U)
226
IRQ Enable Set Register (Mailbox_Irqenable_Set_U) Field Descriptions
229
IRQ Enable Set Register (Mailbox_Irqenable_Set_U)
230
IRQ_ENABLE_SET Register
231
IRQ Enable Clear Register (Mailbox_Irqenable_Clr_U) Field Descriptions
233
IRQ Enable Clear Register (Mailbox_Irqenable_Clr_U)
234
1.14 Spinlock
237
1.14.1 Overview
237
Spinlock Module
237
1.14.2 Integration
238
Spinlock Integration
238
Integration Attributes
238
Clocks and Resets
238
1.14.3 Functional Description
239
Local Power Management Features
239
Spinlock_Lock_Reg_I Register State Diagram
240
Programming Guide
241
Global Initialization of Surrounding Modules
241
Spinlock System Bug Recovery
241
Take and Release Spinlock
242
Spinlock Registers
243
Revision Register (SPINLOCK_REV)
243
Spin Lock Module Registers Offset
243
System Configuration Register (SPINLOCK_SYS_CFG) Field Descriptions
244
System Status Register (SPINLOCK_SYSSTAT) Field Descriptions
245
Lock Register (Spinlock_Lock_Reg_I)
246
Error Location Module
247
Error Location Module Overview
247
ELM Integration
248
Integration Attributes
248
ELM Functional Description
249
Hardware Requests
249
Clocks and Resets
249
Local Power Management Features
249
Events
250
Elm_Location_Status_I Value Decoding Table
251
ELM Basic Programming Model
252
ELM Processing Initialization
252
ELM Processing Completion for Continuous Mode
253
ELM Processing Completion for
253
Use Case: Continuous Mode
254
Use Case
255
ELM Registers
258
ELM Registers Mapping Summary
258
ELM Revision Register (ELM_REVISION)
259
ELM System Configuration Register (ELM_SYSCONFIG)
259
ELM Revision Register (ELM_REVISION) Field Descriptions
259
ELM System Configuration Register (ELM_SYSCONFIG) Field Descriptions
259
ELM System Status Register (ELM_SYSSTATUS)
260
ELM System Status Register (ELM_SYSSTATUS) Field Descriptions
260
ELM Interrupt Status Register (ELM_IRQSTATUS)
261
ELM Interrupt Status Register (ELM_IRQSTATUS) Field Descriptions
261
ELM Interrupt Enable Register (ELM_IRQENABLE)
263
ELM Interrupt Enable Register (ELM_IRQENABLE) Field Descriptions
263
ELM Location Configuration Register (ELM_LOCATION_CONFIG)
264
ELM Location Configuration Register (ELM_LOCATION_CONFIG) Field Descriptions
264
ELM Page Definition Register (ELM_PAGE_CTRL)
265
ELM Page Definition Register (ELM_PAGE_CTRL) Field Descriptions
265
Elm_Syndrome_Fragment_0_I Register
266
Elm_Syndrome_Fragment_1_I Register
266
Elm_Syndrome_Fragment_2_I Register
266
Elm_Syndrome_Fragment_0_I Register Field Descriptions
266
Elm_Syndrome_Fragment_1_I Register Field Descriptions
266
Elm_Syndrome_Fragment_2_I Register Field Descriptions
266
Descriptions
266
1.15.5.11 Elm_Syndrome_Fragment_3_I Register
267
1.15.5.12 Elm_Syndrome_Fragment_4_I Register
267
1.15.5.13 Elm_Syndrome_Fragment_5_I Register
267
Elm_Syndrome_Fragment_3_I Register Field Descriptions
267
Elm_Syndrome_Fragment_4_I Register Field Descriptions
267
Elm_Syndrome_Fragment_5_I Register Field Descriptions
267
1.15.5.14 Elm_Syndrome_Fragment_6_I Register
268
1.15.5.15 Elm_Location_Status_I Register
268
Elm_Syndrome_Fragment_6_I Register Field Descriptions
268
Elm_Location_Status_I Register Field Descriptions
268
1.15.5.16 ELM_ERROR_LOCATION_0-15_I Registers
269
ELM_ERROR_LOCATION_0-15_I Registers Field Descriptions
269
Control Module
270
1.16.1 Registers
270
PLL BOOT Registers
270
Control Status Register (CONTROL_STATUS)
271
Control Status Register (CONTROL_STATUS) Field Descriptions
271
Boot Status Register (BOOTSTAT)
272
Boot Status Register (BOOTSTAT) Field Descriptions
272
DSP Boot Address Register (DSPBOOTADDR)
273
DSP Boot Address Register (DSPBOOTADDR) Field Descriptions
273
PLL Control Registers
274
Main PLL Control Register (MAINPLL_CTRL)
275
Main PLL Control Register (MAINPLL_CTRL) Field Descriptions
275
Main PLL Powerdown Register (MAINPLL_PWD)
276
Main PLL Powerdown Register (MAINPLL_PWD) Field Descriptions
276
Main PLL Frequency 1 Register (MAINPLL_FREQ1)
277
Main PLL Divider 1 Register (MAINPLL_DIV1)
277
Main PLL Frequency 1 Register (MAINPLL_FREQ1) Field Descriptions
277
Main PLL Divider 1 Register (MAINPLL_DIV1) Field Descriptions
277
Main PLL Frequency 2 Register (MAINPLL_FREQ2)
278
Main PLL Divider 2 Register (MAINPLL_DIV2)
278
Main PLL Frequency 2 Register (MAINPLL_FREQ2) Field Descriptions
278
Main PLL Divider 2 Register (MAINPLL_DIV2) Field Descriptions
278
Main PLL Frequency 4 Register (MAINPLL_FREQ4)
279
Main PLL Divider 4 Register (MAINPLL_DIV4)
279
Main PLL Frequency 4 Register (MAINPLL_FREQ4) Field Descriptions
279
Main PLL Divider 4 Register (MAINPLL_DIV4) Field Descriptions
279
Main PLL Frequency 5 Register (MAINPLL_FREQ5)
280
Main PLL Divider 5 Register (MAINPLL_DIV5)
280
Main PLL Frequency 5 Register (MAINPLL_FREQ5) Field Descriptions
280
Main PLL Divider 5 Register (MAINPLL_DIV5) Field Descriptions
280
Main PLL Divider 6 Register (MAINPLL_DIV6)
281
Main PLL Divider 7 Register (MAINPLL_DIV7)
281
Main PLL Divider 6 Register (MAINPLL_DIV6) Field Descriptions
281
Main PLL Divider 7 Register (MAINPLL_DIV7) Field Descriptions
281
DDR PLL Control Register (DDRPLL_CTRL)
282
DDR PLL Control Register (DDRPLL_CTRL) Field Descriptions
282
DDR PLL Powerdown Register (DDRPLL_PWD)
283
DDR PLL Divider 1 Register (DDRPLL_DIV1)
283
DDR PLL Powerdown Register (DDRPLL_PWD) Field Descriptions
283
DDR PLL Divider 1 Register (DDRPLL_DIV1) Field Descriptions
283
DDR PLL Frequency 2 Register (DDRPLL_FREQ2)
284
DDR PLL Divider 2 Register (DDRPLL_DIV2)
284
DDR PLL Frequency 2 Register (DDRPLL_FREQ2) Field Descriptions
284
DDR PLL Divider 2 Register (DDRPLL_DIV2) Field Descriptions
284
DDR PLL Frequency 3 Register (DDRPLL_FREQ3)
285
DDR PLL Divider 3 Register (DDRPLL_DIV3)
285
DDR PLL Frequency 3 Register (DDRPLL_FREQ3) Field Descriptions
285
DDR PLL Divider 3 Register (DDRPLL_DIV3) Field Descriptions
285
DDR PLL Frequency 4 Register (DDRPLL_FREQ4)
286
DDR PLL Divider 4 Register (DDRPLL_DIV4)
286
DDR PLL Frequency 4 Register (DDRPLL_FREQ4) Field Descriptions
286
DDR PLL Divider 4 Register (DDRPLL_DIV4) Field Descriptions
286
DDR PLL Frequency 5 Register (DDRPLL_FREQ5)
287
DDR PLL Divider 5 Register (DDRPLL_DIV5)
287
DDR PLL Frequency 5 Register (DDRPLL_FREQ5) Field Descriptions
287
DDR PLL Divider 5 Register (DDRPLL_DIV5) Field Descriptions
287
Video PLL Control Register (VIDEOPLL_CTRL)
288
Video PLL Control Register (VIDEOPLL_CTRL) Field Descriptions
288
Video PLL Powerdown Register (VIDEOPLL_PWD)
289
Video PLL Powerdown Register (VIDEOPLL_PWD) Field Descriptions
289
Video PLL Frequency 1 Register (VIDEOPLL_FREQ1)
290
Video PLL Divider 1 Register (VIDEOPLL_DIV1)
290
Video PLL Frequency 1 Register (VIDEOPLL_FREQ1) Field Descriptions
290
Video PLL Divider 1 Register (VIDEOPLL_DIV1) Field Descriptions
290
Video PLL Frequency 2 Register (VIDEOPLL_FREQ2)
291
Video PLL Divider 2 Register (VIDEOPLL_DIV2)
291
Video PLL Frequency 2 Register (VIDEOPLL_FREQ2) Field Descriptions
291
Video PLL Divider 2 Register (VIDEOPLL_DIV2) Field Descriptions
291
Video PLL Frequency 3 Register (VIDEOPLL_FREQ3)
292
Video PLL Divider 3 Register (VIDEOPLL_DIV3)
292
Video PLL Frequency 3 Register (VIDEOPLL_FREQ3) Field Descriptions
292
Video PLL Divider 3 Register (VIDEOPLL_DIV3) Field Descriptions
292
Audio PLL Control Register (AUDIOPLL_CTRL)
293
Audio PLL Control Register (AUDIOPLL_CTRL) Field Descriptions
293
Audio PLL Powerdown Register (AUDIOPLL_PWD)
294
Audio PLL Powerdown Register (AUDIOPLL_PWD) Field Descriptions
294
Audio PLL Frequency 2 Register (AUDIOPLL_FREQ2)
295
Audio PLL Divider 2 Register (AUDIOPLL_DIV2)
295
Audio PLL Frequency 2 Register (AUDIOPLL_FREQ2) Field Descriptions
295
Audio PLL Divider 2 Register (AUDIOPLL_DIV2) Field Descriptions
295
Audio PLL Frequency 3 Register (AUDIOPLL_FREQ3)
296
Audio PLL Divider 3 Register (AUDIOPLL_DIV3)
296
Audio PLL Frequency 3 Register (AUDIOPLL_FREQ3) Field Descriptions
296
Audio PLL Divider 3 Register (AUDIOPLL_DIV3) Field Descriptions
296
Audio PLL Frequency 4 Register (AUDIOPLL_FREQ4)
297
Audio PLL Divider 4 Register (AUDIOPLL_DIV4)
297
Audio PLL Frequency 4 Register (AUDIOPLL_FREQ4) Field Descriptions
297
Audio PLL Divider 4 Register (AUDIOPLL_DIV4) Field Descriptions
297
Audio PLL Frequency 5 Register (AUDIOPLL_FREQ5)
298
Audio PLL Divider 5 Register (AUDIOPLL_DIV5)
298
Audio PLL Frequency 5 Register (AUDIOPLL_FREQ5) Field Descriptions
298
Audio PLL Divider 5 Register (AUDIOPLL_DIV5) Field Descriptions
298
Device Configuration Registers
299
Device Identification Register (DEVICE_ID)
300
Device Identification Register (DEVICE_ID) Field Descriptions
300
Initiator Pressure 0 Register (INIT_PRESSURE_0)
301
Initiator Pressure 0 Register (INIT_PRESSURE_0) Field Descriptions
301
Initiator Pressure 1 Register (INIT_PRESSURE_1)
302
Initiator Pressure 1 Register (INIT_PRESSURE_1) Field Descriptions
302
MMU Configuration Register (MMU_CFG)
303
MMU Configuration Register (MMU_CFG) Field Descriptions
303
TPTC Configuration Register (TPTC_CFG)
304
TPTC Configuration Register (TPTC_CFG) Field Descriptions
304
DDR Control Register (DDR_CTRL)
305
DDR Control Register (DDR_CTRL) Field Descriptions
305
DSP Standby/Idle Management Register (DSP_IDLE_CFG)
306
DSP Standby/Idle Management Register (DSP_IDLE_CFG) Field Descriptions
306
USB Control Register (USB_CTRL)
307
USB Control Register (USB_CTRL) Field Descriptions
307
USB Phy Control Register 0 (USBPHY_CTRL0)
308
USB Phy Control Register 0 (USBPHY_CTRL0) Field Descriptions
308
USB Phy Control Register 1 (USBPHY_CTRL1)
309
USB Phy Control Register 1 (USBPHY_CTRL1) Field Descriptions
309
Ethernet MAC ID0 Low Register (MAC_ID0_LO)
310
Ethernet MAC ID0 High Register (MAC_ID0_HI)
310
Ethernet MAC ID0 Low Register (MAC_ID0_LO) Field Descriptions
310
Ethernet MAC ID0 High Register (MAC_ID0_HI) Field Descriptions
310
Ethernet MAC ID1 Low Register (MAC_ID1_LO)
311
Ethernet MAC ID1 High Register (MAC_ID1_HI)
311
Ethernet MAC ID1 Low Register (MAC_ID1_LO) Field Descriptions
311
Ethernet MAC ID1 High Register (MAC_ID1_HI) Field Descriptions
311
PCIE Configuration Register (PCIE_CFG)
312
Clock Control Register (CLK_CTL)
313
Clock Control Register (CLK_CTL) Field Descriptions
313
Audio Interface Control Register (AUD_CTRL)
314
Audio Interface Control Register (AUD_CTRL) Field Descriptions
314
DSP L2 Memory Sleep Mode Register (DSPMEM_SLEEP)
315
DSP L2 Memory Sleep Mode Register (DSPMEM_SLEEP) Field Descriptions
315
On-Chip Memory Sleep Mode Register (OCMEM_SLEEP)
316
On-Chip Memory Sleep Mode Register (OCMEM_SLEEP) Field Descriptions
316
HD DAC Control Register (HD_DAC_CTRL)
317
HD DAC Control Register (HD_DAC_CTRL) Field Descriptions
317
HD DAC a Calibration Register (HD_DACA_CAL)
318
HD DAC B Calibration Register (HD_DACB_CAL)
318
HD DAC a Calibration Register (HD_DACA_CAL) Field Descriptions
318
HD DAC B Calibration Register (HD_DACB_CAL) Field Descriptions
318
HD DAC C Calibration Register (HD_DACC_CAL)
319
SD DAC Control Register (SD_DAC_CTRL)
319
HD DAC C Calibration Register (HD_DACC_CAL) Field Descriptions
319
SD DAC Control Register (SD_DAC_CTRL) Field Descriptions
319
SD DAC a Calibration Register (SD_DACA_CAL)
320
SD DAC B Calibration Register (SD_DACB_CAL)
320
SD DAC a Calibration Register (SD_DACA_CAL) Field Descriptions
320
SD DAC B Calibration Register (SD_DACB_CAL) Field Descriptions
320
SD DAC C Calibration Register (SD_DACC_CAL)
321
SD DAC D Calibration Register (SD_DACD_CAL)
321
SD DAC C Calibration Register (SD_DACC_CAL) Field Descriptions
321
SD DAC D Calibration Register (SD_DACD_CAL) Field Descriptions
321
HW Event Select (Group 1) Register (HW_EVT_SEL_GRP1)
322
HW Event Select (Group 1) Register (HW_EVT_SEL_GRP1) Field Descriptions
322
HW Event Select (Group 2) Register (HW_EVT_SEL_GRP2)
323
HW Event Select (Group 2) Register (HW_EVT_SEL_GRP2) Field Descriptions
323
HW Event Select (Group 3) Register (HW_EVT_SEL_GRP3)
324
HW Event Select (Group 3) Register (HW_EVT_SEL_GRP3) Field Descriptions
324
HW Event Select (Group 4) Register (HW_EVT_SEL_GRP4)
325
HW Event Select (Group 4) Register (HW_EVT_SEL_GRP4) Field Descriptions
325
HDMI Observe Clock Control (HDMI_OBSCLK_CTRL)
326
HDMI Observe Clock Control (HDMI_OBSCLK_CTRL) Field Descriptions
326
Serdes Control Register (SERDES_CTRL)
327
USB Clock Control Register (USB_CLK_CTL)
327
Serdes Control Register (SERDES_CTRL) Field Descriptions
327
USB Clock Control Register (USB_CLK_CTL) Field Descriptions
327
PLL Observe Clock Control Register (PLL_OBSCLK_CTRL)
328
DDR RCD Register (DDR_RCD)
328
PLL Observe Clock Control Register (PLL_OBSCLK_CTRL) Field Descriptions
328
DDR RCD Register (DDR_RCD) Field Descriptions
328
Interrupt Controller
329
Interrupt Controller in Device
329
Resets
330
System-Level Reset Sources
330
DMM/Tiler
331
Introduction
332
Overview
332
DMM Integration
332
2.1.2 Features
333
Functional Block Diagram
333
DMM Block Diagram
333
Terminologies and Acronyms Used in this Document
334
Architecture
335
DMM Functional Description
335
DMM Look-Up Table
337
DMM PAT Direct Access Translation
337
DMM PAT In-Direct Access Translation
338
DMM Section and Memory Mapping
340
512KB and 1KB Interleaving
341
Overview of Request Conversion
342
Memory Map
343
DMM Address Translations
345
TILER Functional Description
346
Image Stored in the Memory Linearly
346
Image Stored in the Memory by TILER
347
Address Space Structure for Tiled Modes
348
4KB Page, 8-Bit Mode
349
4KB Page, 16-Bit Mode
350
4KB Page, 32-Bit Mode
350
Four 1KB Tiles in One 4KB Page
351
Address Format
354
TILER Object Containers and Views
355
Stride for Well-Formed Tiled Mode 2D Block Requests
355
Using LUT to Translate Tiled Virtual Address to Physical SDRC Address
356
Object Container Geometry with 4KB
356
TILER Page Mapping When Using 4KB
357
Isometric Transforms in the TILER Container
358
Paged Mode Addressing
359
TILER Modes Description
359
Tiled Mode Addressing in 0° or 180° Orientations, (S = 0)
360
Tiled Mode Addressing in 90° or 270° Orientations, (S = 1)
360
Tiled Mode Container Characteristics
360
Tiled Mode Ordering of Elements in Natural View
362
Page Mode Ordering of Elements in Natural View
362
Tiled Mode Ordering of Elements in 0° View with Vertical Mirror
363
Page Mode Ordering of Elements in 0° View with Vertical Mirror
363
Tiled Mode Ordering of Elements in 0° View with Horizontal Mirror
364
Page Mode Ordering of Elements in 0° View with Horizontal Mirror
364
Tiled Mode Ordering of Elements in 180° View
365
Page Mode Ordering of Elements in 180° View
365
Tiled Mode Ordering of Elements in 90º View with Vertical Mirror
366
Page Mode Ordering of Elements in 90º View with Vertical Mirror
366
Tiled Mode Ordering of Elements in 270° View
367
Page Mode Ordering of Elements in 270° View
367
Tiled Mode Ordering of Elements in 90° View
368
Page Mode Ordering of Elements in 90° View
368
Tiled Mode Ordering of Elements in 90º View with Horizontal Mirror
369
Page Mode Ordering of Elements in 90º View with Horizontal Mirror
369
Use Case
370
DMM Basic Register Setup
370
Simple LUT Bypass Use Case: Arrangement of Video Buffers
371
Buffer Arrangement for HD Luma Buffers in 128MB 8-Bit Mode Container
371
Buffer Arrangement for HD Chroma Buffers in 128MB 16-Bit Mode Container
372
LUT Refill Using the PAT Refill Engines
373
PAT Descriptor Node
373
PAT Area Description
374
DMM Simple Manual Area Refill
375
DMM Single Auto-Configured Area Refill
376
DMM Chained Auto-Configured Area Refill
377
DMM Synchronised Auto-Configured Area Refill
378
DMM Cyclic Synchronised Auto-Configured Area Refill
379
Address Management Using LISA Sections
380
Case 1 Memory Controllers
381
Controller Configuration
381
Case 2 Memory Controllers
382
Controller Configuration
382
DMM Section Use-Case 2
383
Section Mapping Option
384
Registers
385
DMM Revision Register: DMM_REVISION
385
DMM_REVISION Register
385
DMM/TILER Registers
385
DMM_REVISION Register Field Descriptions
385
DMM Clock Management Configuration: DMM_SYSCONFIG
386
LISA Configuration Locking Register: DMM_LISA_LOCK
386
DMM_SYSCONFIG Register
386
DMM_LISA_LOCK Register
386
DMM_SYSCONFIG Register Field Descriptions
386
DMM_LISA_LOCK Register Field Descriptions
386
DMM LISA MAP Registers: DMM_LISA_MAP_0-DMM_LISA_MAP_3
387
DMM_LISA_MAP Registers
387
DMM_LISA_MAP Registers Field Descriptions
387
DMM TILER Orientation Registers: DMM_TILER_OR0-DMM_TILER_OR1
388
DMM PAT Configuration Register: DMM_PAT_CONFIG
388
DMM_TILER_OR Registers
388
DMM_PAT_CONFIG Register
388
DMM_TILER_OR Registers Field Descriptions
388
DMM_PAT_CONFIG Register Field Descriptions
388
DMM_PAT_VIEW Registers
389
DMM_PAT_VIEW Registers Field Descriptions
389
DMM_PAT_VIEW_MAP Registers
390
DMM_PAT_VIEW_MAP Registers Field Descriptions
390
DMM_PAT_VIEW_MAP_BASE Register
391
DMM_PAT_IRQ_EOI Register
391
DMM_PAT_VIEW_MAP_BASE Register Field Descriptions
391
DMM_PAT_IRQ_EOI Register Field Descriptions
391
DMM_PAT_IRQSTATUS_RAW Register
393
DMM_PAT_IRQSTATUS_RAW Register Field Descriptions
393
DMM_PAT_IRQSTATUS Register
395
DMM_PAT_IRQSTATUS Register Field Descriptions
395
DMM_PAT_IRQENABLE_SET Register
397
DMM_PAT_IRQENABLE_SET Register Field Descriptions
397
DMM_PAT_IRQENABLE_CLR Register
399
DMM_PAT_IRQENABLE_CLR Register Field Descriptions
399
DMM_PAT_STATUS Registers
401
DMM_PAT_STATUS Registers Field Descriptions
401
DMM_PAT_DESCR Registers
402
DMM_PAT_AREA Registers
402
DMM_PAT_DESCR Registers Field Descriptions
402
DMM_PAT_AREA Registers Field Descriptions
402
DMM_PAT_CTRL Registers
403
DMM_PAT_DATA Registers
403
DMM_PAT_CTRL Registers Field Descriptions
403
DMM_PAT_DATA Registers Field Descriptions
403
DMM_PEG_PRIO Registers
404
DMM_PEG_PRIO_PAT Register
404
DMM_PEG_PRIO Registers Field Descriptions
404
DMM_PEG_PRIO_PAT Register Field Descriptions
404
3.1.4 EMAC and MDIO Block Diagram
407
Physical Layer Definitions
409
Ethernet Configuration-GMII Connections
411
EMAC and MDIO Signals for GMII Interface
412
Ethernet Frame Format
413
Ethernet Frame Description
413
Basic Descriptor Format
414
Typical Descriptor Linked List
415
Basic Descriptor Description
415
Transmit Buffer Descriptor Format
418
Receive Buffer Descriptor Format
421
EMAC Control Module Block Diagram
425
EMAC Control Module Interrupts
426
MDIO Module Block Diagram
428
EMAC Module Block Diagram
432
Receive Frame Treatment Summary
442
Middle of Frame Overrun Treatment
443
EMAC Control Module Interrupt Logic Diagram
450
EMAC/MDIO Registers
455
3.3.1 EMAC Control Module Registers
455
EMAC Control Module Identification and Version Register (CMIDVER)
456
EMAC Control Module Software Reset Register (CMSOFTRESET)
456
EMAC Control Module Identification and Version Register (CMIDVER) Field Descriptions
456
EMAC Control Module Software Reset Register (CMSOFTRESET) Field Descriptions
456
Field Descriptions
456
EMAC Control Module Emulation Control Register (CMEMCONTROL)
457
EMAC Control Module Emulation Control Register (CMEMCONTROL) Field Descriptions
457
EMAC Control Module Interrupt Control Register (CMINTCTRL)
458
EMAC Control Module Interrupt Control Register (CMINTCTRL) Field Descriptions
458
EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN)
459
EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
459
EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN) Field Descriptions
459
EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN) Field Descriptions
459
EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)
460
EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN)
460
EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) Field Descriptions
460
EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) Field Descriptions
460
EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT)
461
EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT) Field Descriptions
461
EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)
462
EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT)
462
EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT) Field Descriptions
462
EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) Field Descriptions
462
EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT)
463
EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT) Field Descriptions
463
EMAC Control Module Receive Interrupts Per Millisecond Register (CMRXINTMAX)
464
EMAC Control Module Transmit Interrupts Per Millisecond Register (CMTXINTMAX)
464
EMAC Control Module Receive Interrupts Per Millisecond Register (CMRXINTMAX) Field Descriptions
464
EMAC Control Module Transmit Interrupts Per Millisecond Register (CMTXINTMAX) Field Descriptions
464
3.3.2 Ethernet Media Access Controller (EMAC) Registers
465
Transmit Identification and Version Register (TXIDVER)
468
Transmit Control Register (TXCONTROL)
468
Transmit Identification and Version Register (TXIDVER) Field Descriptions
468
Transmit Control Register (TXCONTROL) Field Descriptions
468
Transmit Teardown Register (TXTEARDOWN)
469
Transmit Teardown Register (TXTEARDOWN) Field Descriptions
469
Receive Identification and Version Register (RXIDVER)
470
Receive Control Register (RXCONTROL)
470
Receive Identification and Version Register (RXIDVER) Field Descriptions
470
Receive Control Register (RXCONTROL) Field Descriptions
470
Receive Teardown Register (RXTEARDOWN)
471
Receive Teardown Register (RXTEARDOWN) Field Descriptions
471
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
472
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions
472
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
473
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions
473
Transmit Interrupt Mask Set Register (TXINTMASKSET)
474
Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
474
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
475
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions
475
MAC Input Vector Register (MACINVECTOR)
476
MAC End of Interrupt Vector Register (MACEOIVECTOR)
476
MAC Input Vector Register (MACINVECTOR) Field Descriptions
476
MAC End of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions
476
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
477
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions
477
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
478
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
478
Receive Interrupt Mask Set Register (RXINTMASKSET)
479
Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions
479
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
480
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions
480
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
481
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
481
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions
481
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions
481
MAC Interrupt Mask Set Register (MACINTMASKSET)
482
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
482
MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions
482
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions
482
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
483
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions
483
Receive Unicast Enable Set Register (RXUNICASTSET)
486
Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
486
Receive Unicast Clear Register (RXUNICASTCLEAR)
487
Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions
487
Receive Maximum Length Register (RXMAXLEN)
488
Receive Buffer Offset Register (RXBUFFEROFFSET)
488
Receive Maximum Length Register (RXMAXLEN) Field Descriptions
488
Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions
488
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
489
Receive Channel N Flow Control Threshold Register (Rxnflowthresh)
489
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions
489
Receive Channel N Flow Control Threshold Register (Rxnflowthresh) Field Descriptions
489
Receive Channel N Free Buffer Count Register (Rxnfreebuffer)
490
Receive Channel N Free Buffer Count Register (Rxnfreebuffer) Field Descriptions
490
MAC Control Register (MACCONTROL)
491
MAC Control Register (MACCONTROL) Field Descriptions
491
MAC Status Register (MACSTATUS)
493
MAC Status Register (MACSTATUS) Field Descriptions
493
Emulation Control Register (EMCONTROL)
495
FIFO Control Register (FIFOCONTROL)
495
Emulation Control
495
Emulation Control Register (EMCONTROL) Field Descriptions
495
FIFO Control Register (FIFOCONTROL) Field Descriptions
495
MAC Configuration Register (MACCONFIG)
496
Soft Reset Register (SOFTRESET)
496
MAC Configuration Register (MACCONFIG) Field Descriptions
496
Soft Reset Register (SOFTRESET) Field Descriptions
496
MAC Source Address Low Bytes Register (MACSRCADDRLO)
497
MAC Source Address High Bytes Register (MACSRCADDRHI)
497
MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions
497
MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions
497
MAC Hash Address Register 1 (MACHASH1)
498
MAC Hash Address Register 2 (MACHASH2)
498
MAC Hash Address Register 1 (MACHASH1) Field Descriptions
498
MAC Hash Address Register 2 (MACHASH2) Field Descriptions
498
Back off Random Number Generator Test Register (BOFFTEST)
499
Transmit Pacing Algorithm Test Register (TPACETEST)
499
Back off Test Register (BOFFTEST) Field Descriptions
499
Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions
499
Receive Pause Timer Register (RXPAUSE)
500
Transmit Pause Timer Register (TXPAUSE)
500
Receive Pause Timer Register (RXPAUSE) Field Descriptions
500
Transmit Pause Timer Register (TXPAUSE) Field Descriptions
500
MAC Address Low Bytes Register (MACADDRLO)
501
MAC Address Low Bytes Register (MACADDRLO) Field Descriptions
501
MAC Address High Bytes Register (MACADDRHI)
502
MAC Index Register (MACINDEX)
502
MAC Address High Bytes Register (MACADDRHI) Field Descriptions
502
MAC Index Register (MACINDEX) Field Descriptions
502
Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp)
503
Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp)
503
Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp) Field Descriptions
503
Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp) Field Descriptions
503
Transmit Channel N Completion Pointer Register (Txncp)
504
Receive Channel N Completion Pointer Register (Rxncp)
504
Transmit Channel N Completion Pointer Register (Txncp) Field Descriptions
504
Receive Channel N Completion Pointer Register (Rxncp) Field Descriptions
504
Statistics Register
505
MDIO Version Register (VERSION)
514
Management Data Input/Output (MDIO) Registers
514
MDIO Version Register (VERSION) Field Descriptions
514
MDIO Control Register (CONTROL)
515
MDIO Control Register (CONTROL) Field Descriptions
515
PHY Acknowledge Status Register (ALIVE)
516
PHY Link Status Register (LINK)
516
PHY Acknowledge Status Register (ALIVE) Field Descriptions
516
PHY Link Status Register (LINK) Field Descriptions
516
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)
517
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions
517
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
518
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions
518
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
519
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions
519
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
520
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions
520
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
521
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions
521
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
522
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field Descriptions
522
MDIO User Access Register 0 (USERACCESS0)
523
MDIO User Access Register 0 (USERACCESS0) Field Descriptions
523
MDIO User PHY Select Register 0 (USERPHYSEL0)
524
MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions
524
MDIO User Access Register 1 (USERACCESS1)
525
MDIO User Access Register 1 (USERACCESS1) Field Descriptions
525
MDIO User PHY Select Register 1 (USERPHYSEL1)
526
MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions
526
GPIO Block Diagram
529
Synchronous Path Block Diagram
529
Interrupt Request Generation
532
Write @ GPIO_CLEARDATAOUT Register Example
534
Write @ Gpio_Setirqenablex Register Example
535
General-Purpose Interface Used as a Keyboard Interface
536
GPIO Registers
537
4.3.1 GPIO_REVISION Register
538
GPIO_REVISION Register Field Descriptions
538
4.3.2 GPIO_SYSCONFIG Register
539
GPIO_SYSCONFIG Register Field Descriptions
539
4.3.3 GPIO_EOI Register
540
GPIO_EOI Register Field Descriptions
540
4.3.4 Gpio_Irqstatus_Raw_N Register
541
4.3.5 Gpio_Irqstatus_N Register
541
Gpio_Irqstatus_Raw_N Register Field Descriptions
541
Gpio_Irqstatus_N Register Field Descriptions
541
4.3.6 Gpio_Irqstatus_Set_N Register
542
4.3.7 Gpio_Irqstatus_Clr_N Register
542
Gpio_Irqstatus_Set_N Register Field Descriptions
542
Gpio_Irqstatus_Clr_N Register Field Descriptions
542
4.3.8 GPIO_SYSSTATUS Register
543
GPIO_SYSSTATUS Register Field Descriptions
543
4.3.9 GPIO_CTRL Register
544
4.3.10 GPIO_OE Register
544
GPIO_CTRL Register Field Descriptions
544
GPIO_OE Register Field Descriptions
544
4.3.11 GPIO_DATAIN Register
545
4.3.12 GPIO_DATAOUT Register
545
GPIO_DATAIN Register Field Descriptions
545
GPIO_DATAOUT Register Field Descriptions
545
4.3.13 GPIO_LEVELDETECT0 Register
546
4.3.14 GPIO_LEVELDETECT1 Register
546
GPIO_LEVELDETECT0 Register Field Descriptions
546
GPIO_LEVELDETECT1 Register Field Descriptions
546
4.3.15 GPIO_RISINGDETECT Register
547
4.3.16 GPIO_FALLINGDETECT Register
547
GPIO_RISINGDETECT Register Field Descriptions
547
GPIO_FALLINGDETECT Register Field Descriptions
547
4.3.17 GPIO_DEBOUNCENABLE Register
548
4.3.18 GPIO_DEBOUNCINGTIME Register
548
GPIO_DEBOUNCENABLE Register Field Descriptions
548
GPIO_DEBOUNCINGTIME Register Field Descriptions
548
4.3.19 GPIO_CLEARDATAOUT Register
549
4.3.20 GPIO_SETDATAOUT Register
549
GPIO_CLEARDATAOUT Register Field Descriptions
549
GPIO_SETDATAOUT Register Field Descriptions
549
GPMC Block Diagram
553
GPMC I/O Description
554
GPMC Pin Multiplexing Options
554
5.2.1 GPMC Signals
554
GPMC to 16-Bit Address/Data-Multiplexed Memory
556
GPMC to 16-Bit Nonmultiplexed Memory
557
GPMC to 8-Bit NAND Device
557
5.2.3 GPMC Integration
558
GPMC Integration Attributes
558
GPMC Clocks and Resets
559
GPMC Hardware Requests
559
GPMC Clocks
560
Gpmc_Config1_I Configuration
560
GPMC Local Power Management Features
560
GPMC Interrupt Events
561
Chip-Select Address Mapping and Decoding Mask
563
Wait Behavior During an Asynchronous Single Read Access (Gpmcfclkdivider = 1)
566
Wait Behavior During a Synchronous Read Burst Access
568
Read to Read for an Address-Data Multiplexed Device, on Different CS, Without Bus Turnaround
570
Attached to Fast Device)
570
Read to Read / Write for an Address-Data Multiplexed Device, on Different CS, with Bus Turnaround
570
Read to Read / Write for a Address-Data or AAD-Multiplexed Device, on same CS, with Bus Turnaround
571
Idle Cycle Insertion Configuration
572
5.2.4.10.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
580
Two Asynchronous Single Read Accesses on an Address/Data Multiplexed Device (32-Bit Read Split into 2 × 16-Bit Read)
581
5.2.4.10.1.1.4 Asynchronous Single Write on an Address/Data-Multiplexed Device
582
5.2.4.10.1.2.2 Asynchronous Single Read on an AAD-Multiplexed Device
584
Asynchronous Single Write on an AAD-Multiplexed Device
585
Synchronous Single Read (GPMCFCLKDIVIDER = 0)
587
Synchronous Single Read (GPMCFCLKDIVIDER = 1)
588
Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 0)
590
Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 1)
591
Synchronous Single Write on an Address/Data-Multiplexed Device
592
Synchronous Multiple Write (Burst Write) in Address/Data-Multiplexed Mode
593
Synchronous Multiple Write (Burst Write) in Address/Address/Data-Multiplexed Mode
594
Asynchronous Single Read on an Address/Data-Nonmultiplexed Device
596
Asynchronous Single Write on an Address/Data-Nonmultiplexed Device
597
Asynchronous Multiple (Page Mode) Read
598
Chip-Select Configuration for NAND Interfacing
601
NAND Command Latch Cycle
603
NAND Address Latch Cycle
604
NAND Data Read Cycle
605
NAND Data Write Cycle
606
Hamming Code Accumulation Algorithm (1 of 2)
610
ECC Enable Settings
610
Hamming Code Accumulation Algorithm (2 of 2)
611
ECC Computation for a 256-Byte Data Stream (Read or Write)
611
ECC Computation for a 512-Byte Data Stream (Read or Write)
612
Word16 ECC Computation
613
Flattened BCH Codeword Mapping (512 Bytes + 104 Bits)
615
Aligned Message Byte Mapping in 8-Bit NAND
615
Aligned Message Byte Mapping in 16-Bit NAND
616
Aligned Nibble Mapping of Message in 8-Bit NAND
616
Misaligned Nibble Mapping of Message in 8-Bit NAND
616
Aligned Nibble Mapping of Message in 16-Bit NAND
616
Misaligned Nibble Mapping of Message in 16-Bit NAND (1 Unused Nibble)
617
Misaligned Nibble Mapping of Message in 16-Bit NAND (2 Unused Nibble)
617
Misaligned Nibble Mapping of Message in 16-Bit NAND (3 Unused Nibble)
617
Manual Mode Sequence and Mapping
618
NAND Page Mapping and ECC: Per-Sector Schemes
623
NAND Page Mapping and ECC: Pooled Spare Schemes
624
NAND Page Mapping and ECC: Per-Sector Schemes, with Separate ECC
625
Prefetch and Write-Posting Engine
626
Prefetch Mode Configuration
628
Write-Posting Mode Configuration
630
NAND Read Cycle Optimization Timing Description
632
Programming Model Top-Level Diagram
634
GPMC Configuration in nor Mode
635
GPMC Configuration in NAND Mode
635
Reset GPMC
635
NOR Memory Type
636
NOR Chip-Select Configuration
636
NOR Timings Configuration
636
WAIT Pin Configuration
636
Enable Chip-Select
636
NAND Memory Type
637
NAND Chip-Select Configuration
637
Asynchronous Read and Write Operations
637
ECC Engine
637
WAIT Pin Configuration
638
Enable Chip-Select
638
Mode Parameters Check List Table
639
Access Type Parameters Check List Table
639
NOR Interfacing Timing Parameters Diagram
640
Timing Parameters
641
NAND Formulas Description Table
643
NAND Command Latch Cycle Timing Simplified Example
644
Synchronous nor Formulas Description Table
644
Synchronous nor Single Read Simplified Example
648
Asynchronous nor Formulas Description Table
649
Asynchronous nor Single Write Simplified Example
650
GPMC Connection to an External nor Flash Memory
652
Useful Timing Parameters on the Memory Side
653
Synchronous Burst Read Access (Timing Parameters in Clock Cycles)
654
Calculating GPMC Timing Parameters
654
AC Characteristics for Asynchronous Read Access
655
Asynchronous Single Read Access (Timing Parameters in Clock Cycles)
656
GPMC Timing Parameters for Asynchronous Read Access
656
AC Characteristics for Asynchronous Single Write (Memory Side)
657
Asynchronous Single Write Access (Timing Parameters in Clock Cycles)
658
GPMC Timing Parameters for Asynchronous Single Write
658
Supported Memory Interfaces
659
NAND Interface Bus Operations Summary
661
NOR Interface Bus Operations Summary
661
GPMC Registers
663
5.5.1 Gpmc_Revision
664
5.5.2 Gpmc_Sysconfig
664
GPMC_REVISION Field Descriptions
664
GPMC_SYSCONFIG Field Descriptions
664
5.5.3 Gpmc_Sysstatus
665
GPMC_SYSSTATUS Field Descriptions
665
5.5.4 Gpmc_Irqstatus
666
GPMC_IRQSTATUS Field Descriptions
666
5.5.5 Gpmc_Irqenable
667
GPMC_IRQENABLE Field Descriptions
667
5.5.6 Gpmc_Timeout_Control
668
5.5.7 Gpmc_Err_Address
668
GPMC_TIMEOUT_CONTROL Field Descriptions
668
GPMC_ERR_ADDRESS Field Descriptions
668
5.5.8 Gpmc_Err_Type
669
GPMC_ERR_TYPE Field Descriptions
669
5.5.9 Gpmc_Config
670
GPMC_CONFIG Field Descriptions
670
5.5.10 Gpmc_Status
671
GPMC_STATUS Field Descriptions
671
5.5.11 Gpmc_Config1_I
672
Gpmc_Config1_I Field Descriptions
672
5.5.12 Gpmc_Config2_I
675
Gpmc_Config2_I Field Descriptions
675
5.5.13 Gpmc_Config3_I
676
Gpmc_Config3_I Field Descriptions
676
5.5.14 Gpmc_Config4_I
678
Gpmc_Config4_I Field Descriptions
678
5.5.15 Gpmc_Config5_I
680
Gpmc_Config5_I Field Descriptions
680
5.5.16 Gpmc_Config6_I
681
Gpmc_Config6_I Field Descriptions
681
5.5.17 Gpmc_Config7_I
682
Gpmc_Config7_I Field Descriptions
682
5.5.18 Gpmc_Nand_Command_I
683
5.5.19 Gpmc_Nand_Address_I
683
5.5.20 Gpmc_Nand_Data_I
683
Gpmc_Nand_Command_I Field Descriptions
683
Gpmc_Nand_Address_I Field Descriptions
683
Gpmc_Nand_Data_I Field Descriptions
683
5.5.21 Gpmc_Prefetch_Config1
684
GPMC_PREFETCH_CONFIG1 Field Descriptions
684
5.5.22 Gpmc_Prefetch_Config2
686
5.5.23 Gpmc_Prefetch_Control
686
GPMC_PREFETCH_CONFIG2 Field Descriptions
686
GPMC_PREFETCH_CONTROL Field Descriptions
686
5.5.24 Gpmc_Prefetch_Status
687
GPMC_PREFETCH_STATUS Field Descriptions
687
5.5.25 Gpmc_Ecc_Config
688
GPMC_ECC_CONFIG Field Descriptions
688
5.5.26 Gpmc_Ecc_Control
689
GPMC_ECC_CONTROL Field Descriptions
689
5.5.27 Gpmc_Ecc_Size_Config
690
GPMC_ECC_SIZE_CONFIG Field Descriptions
690
5.5.28 Gpmc_Eccj_Result
692
Gpmc_Eccj_Result Field Descriptions
692
5.5.29 Gpmc_Bch_Result0_I
693
5.5.30 Gpmc_Bch_Result1_I
693
5.5.31 Gpmc_Bch_Result2_I
693
Gpmc_Bch_Result0_I Field Descriptions
693
Gpmc_Bch_Result1_I Field Descriptions
693
Gpmc_Bch_Result2_I Field Descriptions
693
5.5.32 Gpmc_Bch_Result3_I
694
5.5.33 Gpmc_Bch_Swdata
694
5.5.34 Gpmc_Bch_Result4_I
694
Gpmc_Bch_Result3_I Field Descriptions
694
GPMC_BCH_SWDATA Field Descriptions
694
Gpmc_Bch_Result4_I Field Descriptions
694
5.5.35 Gpmc_Bch_Result5_I
695
5.5.36 Gpmc_Bch_Result6_I
695
Gpmc_Bch_Result5_I Field Descriptions
695
Gpmc_Bch_Result6_I Field Descriptions
695
HDMI Overview
698
HDMI Block Diagram
699
HDMI Video Timings (CEA-861-D)
700
HDMI Video Timings (VESA DMT)
700
HDMI Environment
701
CEC Clock Generation
702
HDMI I/O Signal Description
703
HDMI Integration
704
Integration Attributes
704
Clocks and Resets
705
Hardware Requests
705
Local Power-Management Features
705
HDMI Interrupt Events
706
Video Port Signals
707
HDMI Video Port Mapping
707
HDMI Audio Interface Overview
709
PCM, 16-Bit Format
710
PCM, 24-Bit Format
711
Speaker Mapping Versus Channel
711
Audio Data Stuffing Behavior
713
Audio Data Stuffing Behavior with Only Three Stereo Channels Active
714
IEC 60958 Sample Format
714
IEC 60937 Format
714
6.2.9.2.4.2 L-PCM 16-Bit Format Adaptation
715
Transmitter Video Data Processing Path
717
IP Revision Identifier Register (HDMI_WP_REVISION)
718
HDMI_WP Registers Summary
718
Clock Management Configuration Register (HDMI_WP_SYSCONFIG)
719
Clock Management Configuration Register (HDMI_WP_SYSCONFIG) Field Descriptions
719
Raw Interrupt Status Register (HDMI_WP_IRQSTATUS_RAW)
720
Raw Interrupt Status Register (HDMI_WP_IRQSTATUS_RAW) Field Descriptions
720
Interrupt Status Register (HDMI_WP_IRQSTATUS)
722
Interrupt Status Register (HDMI_WP_IRQSTATUS) Field Descriptions
722
Interrupt Enable Register (HDMI_WP_IRQENABLE_SET)
723
Interrupt Enable Register (HDMI_WP_IRQENABLE_SET) Field Descriptions
723
Interrupt Disable Register (HDMI_WP_IRQENABLE_CLEAR)
725
Interrupt Disable Register (HDMI_WP_IRQENABLE_CLEAR) Field Descriptions
725
Glitch Filter Register (HDMI_WP_DEBOUNCE)
727
Configuration of HDMI Wrapper Video Register (HDMI_WP_VIDEO_CFG)
727
Glitch Filter Register (HDMI_WP_DEBOUNCE) Field Descriptions
727
Configuration of HDMI Wrapper Video Register (HDMI_WP_VIDEO_CFG) Field Descriptions
728
Configuration of Clocks Register (HDMI_WP_CLK)
729
Configuration of Clocks Register (HDMI_WP_CLK) Field Descriptions
729
Audio Configuration in FIFO Register (HDMI_WP_AUDIO_CFG)
730
Audio Configuration in FIFO Register (HDMI_WP_AUDIO_CFG) Field Descriptions
730
Audio Configuration of DMA Register (HDMI_WP_AUDIO_CFG2)
732
Audio FIFO Control Register (HDMI_WP_AUDIO_CTRL)
732
Audio Configuration of DMA Register (HDMI_WP_AUDIO_CFG2) Field Descriptions
732
Audio FIFO Control Register (HDMI_WP_AUDIO_CTRL) Field Descriptions
732
TX Data of FIFO Register (HDMI_WP_AUDIO_DATA)
733
TX Data of FIFO Register (HDMI_WP_AUDIO_DATA) Field Descriptions
733
HDMI_IP_CORE_SYSTEM Registers Summary
734
Vendor ID Register (VND_IDL)
736
Vendor ID Register (VND_IDL) Field Descriptions
736
Vendor ID Register (VND_IDH)
737
Device IDL Register (DEV_IDL)
737
Device IDH Register (DEV_IDH)
737
Vendor ID Register (VND_IDH) Field Descriptions
737
Device IDL Register (DEV_IDL) Field Descriptions
737
Device IDH Register (DEV_IDH) Field Descriptions
737
Device Revision Register (DEV_REV)
738
Device Revision Register (DEV_REV) Field Descriptions
738
Software Reset Register (SRST)
739
System Control Register 1 (SYS_CTRL1)
739
Software Reset Register (SRST) Field Descriptions
739
System Control Register 1 (SYS_CTRL1) Field Descriptions
739
System Status Register (SYS_STAT)
741
System Control Register 3 (SYS_CTRL3)
741
System Status Register (SYS_STAT) Field Descriptions
741
System Control Register 3 (SYS_CTRL3) Field Descriptions
741
Data Control Register (DCTL)
742
Data Control Register (DCTL) Field Descriptions
742
HDCP Control Register (HDCP_CTRL)
743
HDCP Control Register (HDCP_CTRL) Field Descriptions
743
HDCP BKSV Register (BKSV
744
HDCP an Register (an
745
HDCP AKSV Register (AKSV
745
HDCP Ri1 Register (RI1)
745
HDCP Ri Register (RI1) Field Descriptions
745
HDCP Ri2 Register (RI2)
746
HDCP Ri 128 Compare Register (RI_128_COMP)
746
HDCP Ri2 Register (RI2) Field Descriptions
746
HDCP Ri 128 Compare Register (RI_128_COMP) Field Descriptions
746
HDCP I Counter Register (I_CNT)
747
Ri Status Register (RI_STAT)
747
Ri Command Register (RI_CMD)
747
HDCP I Counter Register (I_CNT) Field Descriptions
747
Ri Status Register (RI_STAT) Field Descriptions
747
Ri Line Start Register (RI_START)
748
Ri Command Register (RI_CMD) Field Descriptions
748
Ri Line Start Register (RI_START) Field Descriptions
748
Ri from RX Registers (Low) (RI_RX_L)
749
Ri from RX Registers (High) (RI_RX_H)
749
Ri Debug Registers (RI_DEBUG)
749
Ri from RX Register (Low) (RI_RX_L) Field Descriptions
749
Ri from RX Registers (High) (RI_RX_H) Field Descriptions
749
VIDEO de Delay Register (DE_DLY)
750
Ri Debug Registers (RI_DEBUG) Field Descriptions
750
VIDEO de Delay Register (DE_DLY) Field Descriptions
750
VIDEO de Control Register (DE_CTRL)
751
VIDEO de Top Register (DE_TOP)
751
VIDEO de Control Register (DE_CTRL) Field Descriptions
751
VIDEO de Top Register (DE_TOP) Field Descriptions
751
VIDEO de Count Register (DE_CNTL)
752
VIDEO de Count Register (DE_CNTL) Field Descriptions
752
VIDEO de Count Register (DE_CNTH)
753
VIDEO de Line Register (DE_LINL)
753
VIDEO de Line Register (DE_LINH_1)
753
VIDEO de Count Register (DE_CNTH) Field Descriptions
753
VIDEO de Line Register (DE_LINL) Field Descriptions
753
VIDEO de Line Register (DE_LINH_1) Field Descriptions
753
Video H Resolution Register (HRES_L)
754
Video H Resolution Register (HRES_L) Field Descriptions
754
Video H Resolution Register (HRES_H)
755
Video V Resolution Register (VRES_L)
755
Video V Resolution Register (VRES_H)
755
Video H Resolution Register (HRES_H) Field Descriptions
755
Video V Resolution Low Register (VRES_L) Field Descriptions
755
Video V Resolution Register (VRES_H) Field Descriptions
755
Video Interlace Adjustment Register (IADJUST)
756
Video Interlace Adjustment Register (IADJUST) Field Descriptions
756
Video SYNC Polarity Detection Register (POL_DETECT)
757
Video Hbit to HSYNC Register (HBIT_2HSYNC1)
757
Video SYNC Polarity Detection Register (POL_DETECT) Field Descriptions
757
HBIT_2HSYNC1 Field Descriptions
757
Video Hbit to HSYNC Register (HBIT_2HSYNC2)
758
Video Hbit to HSYNC Register (HBIT_2HSYNC2) Field Descriptions
758
Video Field2 HSYNC Offset Register (FLD2_HS_OFSTL)
759
Video Field2 HSYNC Offset Register (FLD2_HS_OFSTH)
759
Video HSYNC Length Register (HWIDTH1)
759
Video Field2 HSYNC Offset Register (FLD2_HS_OFSTL) Field Descriptions
759
Video Field2 HSYNC Offset Register (FLD2_HS_OFSTH) Field Descriptions
759
Video HSYNC Length Register (HWIDTH1) Field Descriptions
759
Video HSYNC Length Register (HWIDTH2)
760
Video HSYNC Length Register (HWIDTH2) Field Descriptions
760
Video Vbit to VSYNC Register (VBIT_TO_VSYNC)
761
Video VSYNC Length Register (VWIDTH)
761
Video Control Register (VID_CTRL)
761
Video Vbit to VSYNC Register (VBIT_TO_VSYNC) Field Descriptions
761
Video VSYNC Length Register (VWIDTH) Field Descriptions
761
Video Control Register (VID_CTRL) Field Descriptions
762
Video Action Enable Register (VID_ACEN)
763
Video Action Enable Register (VID_ACEN) Field Descriptions
763
Video Mode1 Register (VID_MODE)
764
Video Mode1 Register (VID_MODE) Field Descriptions
764
Video Blanking Register (VID_BLANK1)
765
Video Blanking Register (VID_BLANK2)
765
Video Blanking Register (VID_BLANK3)
765
Video Blanking Registers (VID_BLANK1) Field Descriptions
765
Video Blanking Register (VID_BLANK2) Field Descriptions
765
Video Blanking Register (VID_BLANK3) Field Descriptions
765
Deep Color Header Register (DC_HEADER)
766
Deep Color Header Register (DC_HEADER) Field Descriptions
766
Video Mode2 Register (VID_DITHER)
767
Video Mode2 Register (VID_DITHER) Field Descriptions
767
Rgb_2_Xvycc Control Register (RGB2XVYCC_CT)
768
Rgb_2_Xvycc Control Register (RGB2XVYCC_CT) Field Descriptions
768
Rgb_2_Xvycc Conversion R_2_Y Register (R2Y_COEFF_LOW)
769
Rgb_2_Xvycc Conversion R_2_Y Register (R2Y_COEFF_UP)
769
Rgb_2_Xvycc Conversion G_2_Y Register (G2Y_COEFF_LOW)
769
Rgb_2_Xvycc Conversion R_2_Y Register (R2Y_COEFF_LOW) Field Descriptions
769
Rgb_2_Xvycc Conversion R_2_Y Register (R2Y_COEFF_UP) Field Descriptions
769
Rgb_2_Xvycc Conversion G_2_Y Register (G2Y_COEFF_LOW) Field Descriptions
769
Rgb_2_Xvycc Conversion G_2_Y Register (G2Y_COEFF_UP)
770
Rgb_2_Xvycc Conversion G_2_Y Register (G2Y_COEFF_UP) Field Descriptions
770
Rgb_2_Xvycc Conversion B_2_Y Register (B2Y_COEFF_LOW)
771
Rgb_2_Xvycc Conversion B_2_Y Register (B2Y_COEFF_UP)
771
Rgb_2_Xvycc Conversion R_2_Cb Register (R2CB_COEFF_LOW)
771
Rgb_2_Xvycc Conversion B_2_Y Register (B2Y_COEFF_LOW) Field Descriptions
771
Rgb_2_Xvycc Conversion B_2_Y Register (B2Y_COEFF_UP) Field Descriptions
771
Rgb_2_Xvycc Conversion R_2_Cb Register (R2CB_COEFF_UP)
772
Rgb_2_Xvycc Conversion R_2_Cb Register (R2CB_COEFF_UP) Field Descriptions
772
Rgb_2_Xvycc Conversion G_2_Cb Register (G2CB_COEFF_LOW)
773
Rgb_2_Xvycc Conversion G_2_Cb Register (G2CB_COEFF_UP)
773
Rgb_2_Xvycc Conversion B_2_Cb Register (B2CB_COEFF_LOW)
773
Rgb_2_Xvycc Conversion G_2_Cb Register (G2CB_COEFF_UP) Field Descriptions
773
Rgb_2_Xvycc Conversion B_2_Cb Register (B2CB_COEFF_UP)
774
Rgb_2_Xvycc Conversion B_2_Cb Register (B2CB_COEFF_UP) Field Descriptions
774
Rgb_2_Xvycc Conversion R_2_Cr Register (R2CR_COEFF_LOW)
775
Rgb_2_Xvycc Conversion R_2_Cr Register (R2CR_COEFF_UP)
775
Rgb_2_Xvycc Conversion G_2_Cr Register (G2CR_COEFF_LOW)
775
Rgb_2_Xvycc Conversion R_2_Cr Register (R2CR_COEFF_LOW) Field Descriptions
775
Rgb_2_Xvycc Conversion R_2_Cr Register (R2CR_COEFF_UP) Field Descriptions
775
Rgb_2_Xvycc Conversion G_2_Cr Register (G2CR_COEFF_UP)
776
Rgb_2_Xvycc Conversion G_2_Cr Register (G2CR_COEFF_UP) Field Descriptions
776
Rgb_2_Xvycc Conversion B_2_Cr Register (B2CR_COEFF_LOW)
777
Rgb_2_Xvycc Conversion B_2_Cr Register (B2CR_COEFF_UP)
777
Rgb_2_Xvycc RGB Input Offset Register (RGB_OFFSET_LOW)
777
Rgb_2_Xvycc Conversion B_2_Cr Register (B2CR_COEFF_UP) Field Descriptions
777
Rgb_2_Xvycc RGB Input Offset Register (RGB_OFFSET_LOW) Field Descriptions
777
Rgb_2_Xvycc RGB Input Offset Register (RGB_OFFSET_UP)
778
Rgb_2_Xvycc RGB Input Offset Register (RGB_OFFSET_UP) Field Descriptions
778
Rgb_2_Xvycc Conversion y Output Offset Register (Y_OFFSET_LOW)
779
Rgb_2_Xvycc Conversion y Output Offset Register (Y_OFFSET_UP)
779
Rgb_2_Xvycc Conversion Cbcr Output Offset Register (CBCR_OFFSET_LOW)
779
Rgb_2_Xvycc Conversion Cbcr Output Offset Register (CBCR_OFFSET_UP)
780
Interrupt State Register (INTR_STATE)
781
Interrupt Source Register (INTR1)
781
Interrupt State Register (INTR_STATE) Field Descriptions
781
Interrupt Source Register (INTR1) Field Descriptions
781
Interrupt Source Register (INTR2)
783
Interrupt Source Register (INTR3)
783
Interrupt Source Register (INTR2) Field Descriptions
783
Interrupt Source Register (INTR3) Field Descriptions
784
Interrupt Source Register (INTR4)
785
Interrupt Unmask Register (INT_UNMASK1)
785
Interrupt Source Register (INTR4) Field Descriptions
785
Interrupt Unmask Register (INT_UNMASK1) Field Descriptions
786
Interrupt Unmask Register (INT_UNMASK2)
787
Interrupt Unmask Register (INT_UNMASK3)
787
Interrupt Unmask Register (INT_UNMASK2) Field Descriptions
787
Interrupt Unmask Register (INT_UNMASK3) Field Descriptions
788
Interrupt Unmask Register (INT_UNMASK4)
789
Interrupt Control Register (INT_CTRL)
789
Interrupt Unmask Register (INT_UNMASK4) Field Descriptions
789
Xvycc_2_Rgb Control Register (XVYCC2RGB_CTL)
790
Interrupt Control Register (INT_CTRL) Field Descriptions
790
Xvycc_2_Rgb Control Register (XVYCC2RGB_CTL) Field Descriptions
790
Xvycc_2_Rgb Conversion Y_2_R Register (Y2R_COEFF_LOW)
791
Xvycc_2_Rgb Conversion Y_2_R Register (Y2R_COEFF_UP)
791
Xvycc_2_Rgb Conversion Cr_2_R Register (CR2R_COEFF_LOW)
791
Xvycc_2_Rgb Conversion Y_2_R Register (Y2R_COEFF_LOW) Field Descriptions
791
Xvycc_2_Rgb Conversion Y_2_R Register (Y2R_COEFF_UP) Field Descriptions
791
Xvycc_2_Rgb Conversion Cr_2_R Register (C2R2R_COEFF_UP)
792
Xvycc_2_Rgb Conversion Cr_2_R Register (C2R2R_COEFF_UP) Field Descriptions
792
Xvycc_2_Rgb Conversion Cb_2_B Register (CB2B_COEFF_LOW)
793
Xvycc_2_Rgb Conversion Cb_2_B Register (CB2B_COEFF_UP)
793
Xvycc_2_Rgb Conversion Cr_2_G Register (CR2G_COEFF_LOW)
793
Xvycc_2_Rgb Conversion Cb_2_B Register (CB2B_COEFF_UP) Field Descriptions
793
CR2G_COEFF_LOW Field Descriptions
793
Xvycc_2_Rgb Conversion Cr_2_G Register (CR2G_COEFF_UP)
794
Xvycc_2_Rgb Conversion Cr_2_G Register (CR2G_COEFF_UP) Field Descriptions
794
Xvycc_2_Rgb Conversion Cb_2_G Register (CB2G_COEFF_LOW)
795
Xvycc_2_Rgb Conversion Cb_2_G Register (CB2G_COEFF_UP)
795
Xvycc_2_Rgb Conversion y Offset Register (YOFFSET1_LOW)
795
Xvycc_2_Rgb Conversion Cb_2_G Register (CB2G_COEFF_UP) Field Descriptions
795
Xvycc_2_Rgb Conversion y Offset Register (YOFFSET1_LOW) Field Descriptions
795
Xvycc_2_Rgb Conversion y Offset Register (YOFFSET1_UP)
796
Xvycc_2_Rgb Conversion y Offset Register (YOFFSET1_UP) Field Descriptions
796
Xvycc_2_Rgb Conversion Offset1 Register (OFFSET1_LOW)
797
Xvycc_2_Rgb Conversion Offset1 Register (OFFSET1_MID)
797
Xvycc_2_Rgb Conversion Offset1 Register (OFFSET1_UP)
797
Xvycc_2_Rgb Conversion Offset1 Register (OFFSET1_LOW) Field Descriptions
797
Xvycc_2_Rgb Conversion Offset1 Register (OFFSET1_MID) Field Descriptions
797
Xvycc_2_Rgb Conversion Offset1 Register (OFFSET1_UP) Field Descriptions
797
Xvycc_2_Rgb Conversion Offset2 Register (OFFSET2_LOW)
798
Xvycc_2_Rgb Conversion Offset2 Register (OFFSET2_LOW) Field Descriptions
798
Xvycc_2_Rgb Conversion Offset2 Register (OFFSET2_UP)
799
Xvycc_2_Rgb Conversion DC Level Register (DCLEVEL_LOW)
799
Xvycc_2_Rgb Conversion DC Level Register (DCLEVEL_UP)
799
Xvycc_2_Rgb Conversion Offset2 Register (OFFSET2_UP) Field Descriptions
799
Xvycc_2_Rgb Conversion DC Level Register (DCLEVEL_LOW) Field Descriptions
799
Xvycc_2_Rgb Conversion DC Level Register (DCLEVEL_UP) Field Descriptions
799
DDC I2C Manual Register (DDC_MAN)
800
DDC I2C Manual Register (DDC_MAN) Field Descriptions
800
DDC I2C Target Slave Address Register (DDC_ADDR)
801
DDC I2C Target Segment Address Register (DDC_SEGM)
801
DDC I2C Target Offset Address Register (DDC_OFFSET)
801
DDC I2C Target Slave Address Register (DDC_ADDR) Field Descriptions
801
DDC I2C Target Segment Address Register (DDC_SEGM) Field Descriptions
801
DDC I2C Target Offset Address Register (DDC_OFFSET) Field Descriptions
801
DDC I2C Data Count Register (DDC_COUNT1)
802
DDC I2C Data Count Register (DDC_COUNT1) Field Descriptions
802
DDC I2C Data Count Register (DDC_COUNT2)
803
DDC I2C Status Register (DDC_STATUS)
803
DDC I2C Data Count Register (DDC_COUNT2) Field Descriptions
803
DDC I2C Status Register (DDC_STATUS) Field Descriptions
803
DDC I2C Command Register (DDC_CMD)
804
DDC I2C Data Register (DDC_DATA)
804
DDC I2C Command Register (DDC_CMD) Field Descriptions
804
DDC I2C FIFO Count Register (DDC_FIFOCNT)
805
DDC I2C Data Register (DDC_DATA) Field Descriptions
805
DDC I2C FIFO Count Register (DDC_FIFOCNT) Field Descriptions
805
ROM Status Register (EPST)
806
ROM Command Register (EPCM)
806
ROM Status Register (EPST) Field Descriptions
806
ROM Command Register (EPCM) Field Descriptions
806
Gamut Metadata Register (GAMUT_HEADER1)
808
Gamut Metadata Register (GAMUT_HEADER2)
808
HDMI_IP_CORE_GAMUT Registers Summary
808
Gamut Metadata Register (GAMUT_HEADER1) Field Descriptions
808
Gamut Metadata Register (GAMUT_HEADER2) Field Descriptions
808
Gamut Metadata Register (GAMUT_HEADER3)
810
Gamut Metadata Registers (GAMUT_DBYTE
810
Gamut Metadata Register (GAMUT_HEADER3) Field Descriptions
810
HDMI_IP_CORE_AUDIO_VIDEO Registers Summary
811
ACR Control Register (ACR_CTRL)
812
ACR Control Register (ACR_CTRL) Field Descriptions
812
ACR Audio Frequency Register (FREQ_SVAL)
813
FREQ_SVAL Field Descriptions
813
ACR N Software Value Register (N_SVAL1)
814
ACR N Software Value Register (N_SVAL2)
814
ACR N Software Value Register (N_SVAL1) Field Descriptions
814
ACR N Software Value Register (N_SVAL2) Field Descriptions
814
N_SVAL3 Field Descriptions
814
CTS_SVAL1 Field Descriptions
815
CTS_SVAL2 Field Descriptions
816
CTS_SVAL3 Field Descriptions
816
CTS_HVAL1 Field Descriptions
816
CTS_HVAL2 Field Descriptions
816
CTS_HVAL3 Field Descriptions
817
AUD_MODE Field Descriptions
817
SPDIF_CTRL Field Descriptions
818
HW_SPDIF_FS Field Descriptions
818
SWAP_I2S Field Descriptions
819
SPDIF_ERTH Field Descriptions
819
I2S_IN_MAP Field Descriptions
819
I2S_IN_CTRL Field Descriptions
820
I2S_CHST0 Field Descriptions
820
I2S_CHST1 Field Descriptions
820
I2S_CHST2 Field Descriptions
821
I2S_CHST3 Field Descriptions
821
I2S_CHST4 Field Descriptions
821
I2S_CHST5 Field Descriptions
821
ASRC Field Descriptions
822
I2S_IN_LEN Field Descriptions
822
HDMI_CTRL Field Descriptions
823
AUDO_TXSTAT Field Descriptions
824
AUD_PAR_BUSCLK_1 Field Descriptions
824
AUD_PAR_BUSCLK_2 Field Descriptions
824
AUD_PAR_BUSCLK_3 Field Descriptions
825
TEST_TXCTRL Field Descriptions
825
DPD Field Descriptions
825
PB_CTRL1 Field Descriptions
826
PB_CTRL2 Field Descriptions
827
AVI_TYPE Field Descriptions
828
AVI_VERS Field Descriptions
828
AVI_LEN Field Descriptions
828
AVI_CHSUM Field Descriptions
828
Avi_Dbyte
829
SPD_TYPE Field Descriptions
829
SPD_VERS Field Descriptions
829
SPD_LEN Field Descriptions
829
SPD_CHSUM Field Descriptions
830
Spd_Dbyte
830
AUDIO_TYPE Field Descriptions
830
AUDIO_VERS Field Descriptions
830
AUDIO_LEN Field Descriptions
831
AUDIO_CHSUM Field Descriptions
831
Audio_Dbyte
831
MPEG_TYPE Field Descriptions
831
MPEG_VERS Field Descriptions
832
MPEG_LEN Field Descriptions
832
MPEG_CHSUM Field Descriptions
832
Mpeg_Dbyte
832
Gen_Dbyte
833
CP_BYTE1 Field Descriptions
833
CEC_ADDR_ID Field Descriptions
833
HDMI_IP_CORE_CEC Registers Summary
834
CEC_DEV_ID Field Descriptions
834
CEC_SPEC Field Descriptions
834
CEC_SUFF Field Descriptions
835
CEC_FW Field Descriptions
835
CEC_DBG_0 Field Descriptions
835
CEC_DBG_1 Field Descriptions
835
CEC_DBG_2 Field Descriptions
836
CEC_DBG_3 Field Descriptions
836
CEC_TX_INIT Field Descriptions
836
CEC_TX_DEST Field Descriptions
837
CEC_SETUP Field Descriptions
837
CEC_TX_COMMAND Field Descriptions
837
Cec_Tx_Operand
837
CEC_TRANSMIT_DATA Field Descriptions
838
CEC_CA_7_0 Field Descriptions
838
CEC_CA_15_8 Field Descriptions
838
CEC_INIT_ENABLE_0 Field Descriptions
839
CEC_INIT_ENABLE_1 Field Descriptions
839
CEC_INIT_STATUS_0 Field Descriptions
840
CEC_INIT_STATUS1 Field Descriptions
840
CEC_RX_CONTROL Field Descriptions
841
CEC_RX_COUNT Field Descriptions
841
CEC_RX_CMD_HEADER Field Descriptions
841
CEC_RX_COMMAND Field Descriptions
841
Cec_Rx_Operand
842
HDMI_PHY Registers Summary
843
TMDS_CNTL2 Field Descriptions
843
TMDS_CNTL3 Field Descriptions
843
BIST_CNTL Field Descriptions
844
TMDS_CNTL9 Field Descriptions
844
I2C Functional Block Diagram
846
Multiple I2C Modules Connected
847
Bit Transfer on the I2C Bus
848
Signal Pads
848
Reset State of I2C Signals
848
Start and Stop Condition Events
849
I2C Data Transfer
849
I2C Data Transfer Formats
850
Arbitration Procedure between Two Master Transmitters
851
Synchronization of Two I2C Clock Generators
851
Receive FIFO Interrupt Request Generation
853
Transmit FIFO Interrupt Request Generation
854
Receive FIFO DMA Request Generation
855
Transmit FIFO DMA Request Generation (High Threshold)
855
Transmit FIFO DMA Request Generation (Low Threshold)
856
I2C Registers
858
Module Revision Register (LOW BYTES) (I2C_REVNB_LO)
859
Module Revision Register (LOW BYTES) (I2C_REVNB_LO) Field Descriptions
859
Module Revision Register (HIGH BYTES) (I2C_REVNB_HI)
860
Module Revision Register (HIGH BYTES) (I2C_REVNB_HI) Field Descriptions
860
System Configuration Register (I2C_SYSC)
861
System Configuration Register (I2C_SYSC) Field Descriptions
861
I2C End of Interrupt Register (I2C_EOI)
862
I2C Status Raw Register (I2C_IRQSTATUS_RAW)
862
I2C End of Interrupt Register (I2C_EOI) Field Descriptions
862
I2C Status Raw Register (I2C_IRQSTATUS_RAW) Field Descriptions
862
I2C Status Register (I2C_IRQSTATUS)
867
I2C Status Register (I2C_IRQSTATUS) Field Descriptions
867
I2C Interrupt Enable Set Register (I2C_IRQENABLE_SET)
869
I2C Interrupt Enable Set Register (I2C_IRQENABLE_SET) Field Descriptions
869
I2C Interrupt Enable Clear Register (I2C_IRQENABLE_CLR)
871
I2C Interrupt Enable Clear Register (I2C_IRQENABLE_CLR) Field Descriptions
871
I2C Wakeup Enable Register (I2C_WE)
873
I2C Wakeup Enable Register (I2C_WE) Field Descriptions
873
Receive DMA Enable Set Register (I2C_DMARXENABLE_SET)
876
Receive DMA Enable Set Register (I2C_DMATXENABLE_SET)
876
Receive DMA Enable Set Register (I2C_DMARXENABLE_SET) Field Descriptions
876
Transmit DMA Enable Set Register (I2C_DMATXENABLE_SET) Field Descriptions
876
Receive DMA Enable Set Register (I2C_DMARXENABLE_CLR)
877
Receive DMA Enable Set Register (I2C_DMATXENABLE_CLR)
877
Receive DMA Enable Clear Register (I2C_DMARXENABLE_CLR) Field Descriptions
877
Transmit DMA Enable Clear Register (I2C_DMATXENABLE_CLR) Field Descriptions
877
Receive DMA Wakeup Register (I2C_DMARXWAKE_EN)
878
Receive DMA Wakeup Register (I2C_DMARXWAKE_EN) Field Descriptions
878
Receive DMA Wakeup Register (I2C_DMATXWAKE_EN)
880
Transmit DMA Wakeup Register (I2C_DMATXWAKE_EN) Field Descriptions
880
System Status Register (I2C_SYSS)
882
Buffer Configuration Register (I2C_BUF)
882
System Status Register (I2C_SYSS) Field Descriptions
882
Buffer Configuration Register (I2C_BUF) Field Descriptions
882
Data Counter Register (I2C_CNT)
884
Data Counter Register (I2C_CNT) Field Descriptions
884
Data Access Register (I2C_DATA)
885
Data Access Register (I2C_DATA) Field Descriptions
885
I2C Configuration Register (I2C_CON)
886
I2C Configuration Register (I2C_CON) Field Descriptions
886
I2C Own Address Register (I2C_OA)
888
I2C Own Address Register (I2C_OA) Field Descriptions
888
I2C Own Address Register (I2C_SA)
889
I2C Slave Address Register (I2C_SA) Field Descriptions
889
I2C Own Address Register (I2C_PSC)
890
Clock Divider
890
I2C Clock Prescaler Register (I2C_PSC) Field Descriptions
890
I2C SCL Low Time Register (I2C_SCLL)
891
I2C SCL High Time Register (I2C_SCLH)
891
I2C SCL Low Time Register (I2C_SCLL) Field Descriptions
891
I2C SCL High Time Register (I2C_SCLH) Field Descriptions
891
System Test Register (I2C_SYSTEST)
892
System Test Register (I2C_SYSTEST) Field Descriptions
892
I2C Buffer Status Register (I2C_BUFSTAT)
895
I2C Buffer Status Register (I2C_BUFSTAT) Field Descriptions
895
Own Address 1 (OA1) (I2C_OA1)
896
Own Address 1 (OA1) (I2C_OA1) Field Descriptions
896
I2C Own Address 2 Register (I2C_OA2)
897
I2C Own Address 2 Register (I2C_OA2) Field Descriptions
897
I2C Own Address 3 Register (I2C_OA3)
898
I2C Own Address 3 Register (I2C_OA3) Field Descriptions
898
Active Own Address Register (I2C_ACTOA)
899
Active Own Address Register (I2C_ACTOA) Field Descriptions
899
I2C Clock Blocking Enable Register (I2C_SBLOCK)
900
I2C Clock Blocking Enable Register (I2C_SBLOCK) Field Descriptions
900
Interrupt Controller
902
Interrupt Controller Block Diagram
903
ARM A8 Subsystem INTC Integration
904
Interrupt Controller Resets
905
Interrupt Controller Interrupt Inputs and Outputs
905
IRQ/FIQ Processing Sequence
911
Nested IRQ/FIQ Processing Sequence
915
Interrupt Controller (INTC) Registers
917
8.4.1 INTCPS_REVISION Register
918
8.4.2 INTCPS_SYSCONFIG Register
918
INTCPS_REVISION Register Field Descriptions
918
INTCPS_SYSCONFIG Register Field Descriptions
918
8.4.3 INTCPS_SYSSTATUS Register
919
8.4.4 INTCPS_SIR_IRQ Register
919
INTCPS_SYSSTATUS Register Field Descriptions
919
INTCPS_SIR_IRQ Register Field Descriptions
919
8.4.5 INTCPS_SIR_FIQ Register
920
8.4.6 INTCPS_CONTROL Register
920
INTCPS_SIR_FIQ Register Field Descriptions
920
INTCPS_CONTROL Register Field Descriptions
920
8.4.7 INTCPS_PROTECTION Register
921
8.4.8 INTCPS_IDLE Register
921
INTCPS_PROTECTION Register Field Descriptions
921
INTCPS_IDLE Register Field Descriptions
921
8.4.9 INTCPS_IRQ_PRIORITY Register
922
8.4.10 INTCPS_FIQ_PRIORITY Register
922
INTCPS_IRQ_PRIORITY Register Field Descriptions
922
INTCPS_FIQ_PRIORITY Register Field Descriptions
922
8.4.11 INTCPS_THRESHOLD Register
923
Intcps_Itrn Register
923
INTCPS_THRESHOLD Register Field Descriptions
923
Intcps_Itrn Register Field Descriptions
923
Intcps_Mirn Register
924
Intcps_Mir_Clearn Register
924
Intcps_Mir_Setn Register
924
Intcps_Mirn Register Field Descriptions
924
Intcps_Mir_Clearn Register Field Descriptions
924
Intcps_Mir_Setn Register Field Descriptions
924
Intcps_Isr_Setn Register
925
Intcps_Isr_Clearn Register
925
Intcps_Pending_Irqn Register
925
Intcps_Isr_Setn Register Field Descriptions
925
Intcps_Isr_Clearn Register Field Descriptions
925
Intcps_Pending_Irqn Register Field Descriptions
925
Intcps_Pending_Fiqn Register
926
Intcps_Ilrm Register
926
Intcps_Pending_Fiqn Register Field Descriptions
926
Intcps_Ilrm Register Field Descriptions
926
SD/SDIO1 Overview
928
SD1 Connectivity to an SD Card
930
SD/SDIO Controller Pins and Descriptions
930
Command Token Format
931
48-Bit Response Packet (R1, R3, R4, R5, R6)
932
136-Bit Response Packet (R2)
932
Response Type Summary
932
Data Packet for Sequential Transfer (1-Bit)
933
Data Packet for Block Transfer (1-Bit)
933
Data Packet for Block Transfer (4-Bit)
933
Local Power Management Features
936
Clock Activity Settings
936
9.2.5.1.1 DMA Receive Mode
940
9.2.5.1.2 DMA Transmit Mode
941
Buffer Management for a Write
943
Buffer Management for a Read
944
Memory Size, BLEN, and Buffer Relationship
944
SD, SDIO Responses in the Sd_Rspxx Registers
945
CC and TC Values Upon Error Detected
946
Busy Timeout for R1B, R5B Responses
947
Busy Timeout after Write CRC Status
947
Write CRC Status Timeout
948
Read Data Timeout
948
Boot Acknowledge Timeout When Using CMD0
949
Boot Acknowledge Timeout When CMD Held Low
949
Auto CMD12 Timing During Write Transfer
950
Auto Command 12 Timings During Read Transfer
951
SD/SDIO Controller Transfer Stop Command Summary
952
Output Driven on Falling Edge
953
Output Driven on Rising Edge
953
Boot Mode with CMD0
954
Boot Mode with CMD Line Tied to 0
954
9.2.15 SD/SDIO Hardware Status Features
956
Global Init for Surrounding Modules
957
SD/SDIO Controller Software Reset Flow
958
SD/SDIO Controller Wake-Up Configuration
958
SD/SDIO Controller Bus Configuration Flow
959
SD/SDIO Controller Card Identification and Selection - Part 1
960
SD/SDIO Controller Card Identification and Selection - Part 2
961
SD/SDIO Registers
962
SD_HL_REV Register
963
SD_HL_HWINFO Register
963
SD_HL_SYSCONFIG Register
963
System Configuration Register (SD_SYSCONFIG)
964
System Configuration Register (SD_SYSCONFIG) Field Descriptions
964
System Status Register (SD_SYSSTATUS)
966
Card Status Response Error (SD_CSRE)
966
System Status Register (SD_SYSSTATUS) Field Descriptions
966
Card Status Response Error (SD_CSRE) Field Descriptions
966
System Test Register (SD_SYSTEST)
967
System Test Register (SD_SYSTEST) Field Descriptions
967
Configuration Register (SD_CON)
970
Configuration Register (SD_CON) Field Descriptions
970
Power Counter Register (SD_PWCNT)
973
Card Status Response Error (SD_SDMASA)
973
Power Counter Register (SD_PWCNT) Field Descriptions
973
Card Status Response Error (SD_SDMASA) Field Descriptions
973
Transfer Length Configuration Register (SD_BLK)
974
Transfer Length Configuration Register (SD_BLK) Field Descriptions
974
Command Argument Register (SD_ARG)
975
Command and Transfer Mode Register (SD_CMD)
975
Command Argument Register (SD_ARG) Field Descriptions
975
Command and Transfer Mode Register (SD_CMD) Field Descriptions
976
Command Response[31:0] Register (SD_RSP10)
979
Command Response[63:32] Register (SD_RSP32)
979
Command Response[31:0] Register (SD_RSP10) Field Descriptions
979
Command Response[63:32] Register (SD_RSP32) Field Descriptions
979
Command Response[95:64] Register (SD_RSP54)
980
Command Response[127:96] Register (SD_RSP76)
980
Command Response[95:64] Register (SD_RSP54) Field Descriptions
980
Command Response[127:96] Register (SD_RSP76) Field Descriptions
980
Data Register (SD_DATA)
981
Data Register (SD_DATA) Field Descriptions
981
Present State Register (SD_PSTATE)
982
Present State Register (SD_PSTATE) Field Descriptions
982
Control Register (SD_HCTL)
985
Control Register (SD_HCTL) Field Descriptions
985
SD System Control Register (SD_SYSCTL)
988
SD System Control Register (SD_SYSCTL) Field Descriptions
988
Interrupt Status Register (SD_STAT)
990
Interrupt Status Register (SD_STAT) Field Descriptions
990
Interrupt SD Enable Register (SD_IE)
995
Interrupt SD Enable Register (SD_IE) Field Descriptions
995
Interrupt Signal Enable Register (SD_ISE)
998
Interrupt Signal Enable Register (SD_ISE) Field Descriptions
998
Auto CMD12 Error Status Register (SD_AC12)
1001
Auto CMD12 Error Status Register (SD_AC12) Field Descriptions
1001
Capabilities Register (SD_CAPA)
1002
Capabilities Register (SD_CAPA) Field Descriptions
1002
Maximum Current Capabilities Register (SD_CUR_CAPA)
1004
Maximum Current Capabilities Register (SD_CUR_CAPA) Field Descriptions
1004
Interrupt Signal Enable Register (SD_ISE)
1005
Force Event Register (SD_FE) Field Descriptions
1005
ADMA Error Status Register (SD_ADMAES)
1007
ADMA Error Status Register (SD_ADMAES) Field Descriptions
1007
ADMA System Address Low Bits (SD_ADMASAL)
1008
ADMA System Address High Bits Register (SD_ADMASAH)
1008
ADMA System Address Low Bits (SD_ADMASAL) Field Descriptions
1008
ADMA System Address High Bits Register (SD_ADMASAH) Field Descriptions
1008
Versions Register (SD_REV)
1009
Versions Register (SD_REV) Field Descriptions
1009
Mcasp Block Diagram
1014
Mcasp to Parallel 2-Channel Dacs
1015
Mcasp to 6-Channel DAC and 2-Channel DAC
1015
Mcasp to Digital Amplifier
1016
Mcasp as Digital Audio Encoder
1016
Mcasp as 16 Channel Digital Processor
1016
TDM Format-6 Channel TDM Example
1017
TDM Format Bit Delays from Frame Sync
1018
10.1.6.1.2 Inter-Integrated Sound (I2S) Format
1018
Biphase-Mark Code (BMC)
1019
Biphase-Mark Encoder
1019
S/PDIF Subframe Format
1020
Preamble Codes
1020
S/PDIF Frame Format
1021
Definition of Bit, Word, and Slot
1022
Bit Order and Word Alignment Within a Slot Examples
1022
Definition of Frame and Frame Sync Width
1023
Transmit Clock Generator Block Diagram
1025
Receive Clock Generator Block Diagram
1026
Frame Sync Generator Block Diagram
1027
Mcasp Interface Signals
1028
Burst Frame Sync Mode
1029
Transmit DMA Event (AXEVT) Generation in TDM Time Slots
1031
Channel Status and User Data for each DIT Block
1035
Individual Serializer and Connections Within Mcasp
1036
Receive Format Unit
1037
Transmit Format Unit
1037
Mcasp I/O Pin Control Block Diagram
1039
Processor Service Time Upon Transmit DMA Event (AXEVT)
1041
Processor Service Time Upon Receive DMA Event (AREVT)
1042
Mcasp Audio FIFO (AFIFO) Block Diagram
1044
Transmit Bitstream Data Alignment
1047
Data Flow through Transmit Format Unit, Illustrated
1048
Receive Bitstream Data Alignment
1049
Data Flow through Receive Format Unit, Illustrated
1050
Transmit Clock Failure Detection Circuit Block Diagram
1054
Receive Clock Failure Detection Circuit Block Diagram
1056
Serializers in Loopback Mode
1057
10.2.11.1 Interrupt Multiplexing
1062
Audio Mute (AMUTE) Block Diagram
1063
DMA Events in an Audio Example-Two Events (Scenario 1)
1065
DMA Events in an Audio Example-Four Events (Scenario 2)
1065
DMA Events in an Audio Example
1066
Mcasp Registers Accessed through Configuration Bus
1067
Mcasp Registers Accessed through Data Port
1069
Revision Identification Register (REV)
1070
Mcasp AFIFO Registers Accessed through Peripheral Configuration Port
1070
Revision Identification Register (REV) Field Descriptions
1070
Pin Function Register (PFUNC)
1071
Pin Function Register (PFUNC) Field Descriptions
1072
Pin Direction Register (PDIR)
1073
Pin Direction Register (PDIR) Field Descriptions
1074
Pin Data Output Register (PDOUT)
1075
Pin Data Output Register (PDOUT) Field Descriptions
1076
Pin Data Input Register (PDIN)
1077
Pin Data Input Register (PDIN) Field Descriptions
1078
Pin Data Set Register (PDSET)
1079
Pin Data Set Register (PDSET) Field Descriptions
1080
Pin Data Clear Register (PDCLR)
1081
Pin Data Clear Register (PDCLR) Field Descriptions
1082
Global Control Register (GBLCTL)
1083
Global Control Register (GBLCTL) Field Descriptions
1083
Audio Mute Control Register (AMUTE)
1085
Audio Mute Control Register (AMUTE) Field Descriptions
1085
Digital Loopback Control Register (DLBCTL)
1087
Digital Loopback Control Register (DLBCTL) Field Descriptions
1087
Digital Mode Control Register (DITCTL)
1088
Digital Mode Control Register (DITCTL) Field Descriptions
1088
Receiver Global Control Register (RGBLCTL)
1089
Receiver Global Control Register (RGBLCTL) Field Descriptions
1089
Receive Format Unit Bit Mask Register (RMASK)
1090
Receive Format Unit Bit Mask Register (RMASK) Field Descriptions
1090
Receive Bit Stream Format Register (RFMT)
1091
Receive Bit Stream Format Register (RFMT) Field Descriptions
1091
Receive Frame Sync Control Register (AFSRCTL)
1093
Receive Frame Sync Control Register (AFSRCTL) Field Descriptions
1093
Receive Clock Control Register (ACLKRCTL)
1094
Receive Clock Control Register (ACLKRCTL) Field Descriptions
1094
Receive High-Frequency Clock Control Register (AHCLKRCTL)
1095
Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions
1095
Receive TDM Time Slot Register (RTDM)
1096
Receive TDM Time Slot Register (RTDM) Field Descriptions
1096
Receiver Interrupt Control Register (RINTCTL)
1097
Receiver Interrupt Control Register (RINTCTL) Field Descriptions
1097
Receiver Status Register (RSTAT)
1098
Receiver Status Register (RSTAT) Field Descriptions
1098
Current Receive TDM Time Slot Registers (RSLOT)
1099
Current Receive TDM Time Slot Registers (RSLOT) Field Descriptions
1099
Receive Clock Check Control Register (RCLKCHK)
1100
Receive Clock Check Control Register (RCLKCHK) Field Descriptions
1100
Receiver DMA Event Control Register (REVTCTL)
1101
Receiver DMA Event Control Register (REVTCTL) Field Descriptions
1101
Transmitter Global Control Register (XGBLCTL)
1102
Transmitter Global Control Register (XGBLCTL) Field Descriptions
1102
Transmit Format Unit Bit Mask Register (XMASK)
1103
Transmit Format Unit Bit Mask Register (XMASK) Field Descriptions
1103
Transmit Bit Stream Format Register (XFMT)
1104
Transmit Bit Stream Format Register (XFMT) Field Descriptions
1104
Transmit Frame Sync Control Register (AFSXCTL)
1106
Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions
1106
Transmit Clock Control Register (ACLKXCTL)
1107
Transmit Clock Control Register (ACLKXCTL) Field Descriptions
1107
Transmit High-Frequency Clock Control Register (AHCLKXCTL)
1108
Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Descriptions
1108
Transmit TDM Time Slot Register (XTDM)
1109
Transmit TDM Time Slot Register (XTDM) Field Descriptions
1109
Transmitter Interrupt Control Register (XINTCTL)
1110
Transmitter Interrupt Control Register (XINTCTL) Field Descriptions
1110
Transmitter Status Register (XSTAT)
1111
Transmitter Status Register (XSTAT) Field Descriptions
1111
Current Transmit TDM Time Slot Register (XSLOT)
1112
Current Transmit TDM Time Slot Register (XSLOT) Field Descriptions
1112
Transmit Clock Check Control Register (XCLKCHK)
1113
Transmit Clock Check Control Register (XCLKCHK) Field Descriptions
1113
Transmitter DMA Event Control Register (XEVTCTL)
1114
Transmitter DMA Event Control Register (XEVTCTL) Field Descriptions
1114
Serializer Control Registers (Srctln)
1115
Serializer Control Registers (Srctln) Field Descriptions
1115
DIT Left Channel Status Registers (DITCSRA0-DITCSRA5)
1116
DIT Right Channel Status Registers (DITCSRB0-DITCSRB5)
1116
DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5)
1116
DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5)
1116
Transmit Buffer Registers (Xbufn)
1117
Receive Buffer Registers (Rbufn)
1117
Write FIFO Control Register (WFIFOCTL)
1118
Write FIFO Control Register (WFIFOCTL) Field Descriptions
1118
Write FIFO Status Register (WFIFOSTS)
1119
Write FIFO Status Register (WFIFOSTS) Field Descriptions
1119
Read FIFO Control Register (RFIFOCTL)
1120
Read FIFO Control Register (RFIFOCTL) Field Descriptions
1120
Read FIFO Status Register (RFIFOSTS)
1121
Read FIFO Status Register (RFIFOSTS) Field Descriptions
1121
Mcbsp Block Diagram
1125
Mcbsp Data Transfer Paths
1126
Clock Signal Control of Bit Transfer Timing
1127
Mcbsp Operating at Maximum Packet Frequency
1128
Phases, Words and Bits Per Frame Control Bits
1129
Single-Phase Frame for a Mcbsp Data Transfer
1130
Dual-Phase Frame for a Mcbsp Data Transfer
1130
Mcbsp Reception Physical Data Path
1131
Mcbsp Reception Signal Activity
1131
Mcbsp Transmission Physical Data Path
1132
Mcbsp Transmission Signal Activity
1132
Sample Rate Generator Block Diagram
1133
Effects of DLB and ALB Bits on Clock Modes
1134
CLKG Synchronization and FSG Generation (GSYNC = 1 and CLKGDV = 1)
1137
CLKG Synchronization and FSG Generation (GSYNC = 1 and CLKGDV = 3H)
1137
Overrun in the Mcbsp Receiver
1139
Unexpected Frame-Sync Pulse During a Mcbsp Reception
1140
Proper Positioning of Receive Frame-Sync Pulses
1141
Unexpected Frame-Sync Pulse During a Mcbsp Transmission
1142
Proper Positioning of Transmit Frame-Sync Pulses
1143
Channels, Block, Partitions
1144
Mcbsp Data Transfer in the 8-Partition Mode
1145
Eight Partitions - Receive Channel Assignment and Control
1145
Eight Partitions - Transmit Channel Assignment and Control
1145
Alternating between Partitions a and B Channels
1147
Selecting a Transmit Multichannel Selection Mode with the XMCM Bit Field
1147
Mcbsp Channel Control Options
1148
Activity on Mcbsp Pins for the Possible Values of XMCM Bit
1149
11.2.6.1 Transmit Full Cycle Mode
1151
11.2.6.2 Transmit Half Cycle Mode
1151
11.2.6.3 Receive Full Cycle Mode
1152
11.2.6.4 Receive Half Cycle Mode
1152
11.2.7.2.1 Analysis of the Receiver Smart Idle Behavior
1154
Input Clock Selection for Sample Rate Generator
1156
Range of Programmable Data Delay
1160
How to Calculate the Length of the Receive Frame
1160
2-Bit Data Delay Used to Skip a Framing Bit
1161
Example: Use of RJUST Bit Field with 12-Bit Data Value Abch
1161
Example: Use of RJUST Bit Field with 20-Bit Data Value ABCDE
1161
FSRM and GSYNC Effects on Frame-Sync Signal and Mcbsp.fsr Pin
1162
Data Externally Clocked on a Rising Edge and Sampled on a Falling Edge
1163
Frame of 16 CLKG Periods and Active Width of 2 CLKG Periods
1164
CLKRM Effect on Receive Clock Signal and Mcbsp.clkr Pin
1164
How to Calculate the Length of the Transmit Frame
1168
Range of Programmable Data Delay
1169
2-Bit Data Delay Used to Skip a Framing Bit
1169
How FSXM and FSGM Select the Source of Transmit Frame-Sync Pulses
1170
Frame of 16 CLKG Periods and Active Width of 2 CLKG Periods
1172
CLKXM Bit Effect on Transmit Clock and Mcbsp.clkx Pin
1172
Using Mcbsp Pins for General-Purpose I/O
1175
Mcbsp Registers
1176
Mcbsp_Drr_Reg
1177
Mcbsp_Drr_Reg Field Descriptions
1177
Mcbsp_Dxr_Reg Field Descriptions
1177
Mcbsp_Spcr2_Reg
1178
Mcbsp_Spcr2_Reg Field Descriptions
1178
Mcbsp_Spcr1_Reg
1180
Mcbsp_Spcr1_Reg Field Descriptions
1180
Mcbsp_Rcr2_Reg
1181
Mcbsp_Rcr2_Reg Field Descriptions
1181
Mcbsp_Rcr1_Reg
1182
Mcbsp_Rcr1_Reg Field Descriptions
1182
Mcbsp_Xcr2_Reg
1183
Mcbsp_Xcr2_Reg Field Descriptions
1183
Mcbsp_Xcr1_Reg
1184
Mcbsp_Xcr1_Reg Field Descriptions
1184
Mcbsp_Srgr2_Reg
1185
Mcbsp_Srgr2_Reg Field Descriptions
1185
Mcbsp_Srgr1_Reg
1186
Mcbsp_Srgr1_Reg Field Descriptions
1186
Mcbsp_Mcr2_Reg
1187
Mcbsp_Mcr2_Reg Field Descriptions
1188
Mcbsp_Mcr1_Reg
1189
Mcbsp_Rcera_Reg
1190
Mcbsp_Rcerb_Reg
1190
Mcbsp_Mcr1_Reg Field Descriptions
1190
Mcbsp_Xcera_Reg
1191
Mcbsp_Xcerb_Reg
1191
Mcbsp_Pcr_Reg
1192
Mcbsp_Pcr_Reg Field Descriptions
1193
Mcbsp_Rcerc_Reg
1194
Mcbsp_Rcerd_Reg
1194
Mcbsp_Xcerc_Reg
1195
Mcbsp_Xcerd_Reg
1195
Mcbsp_Rcere_Reg
1196
Mcbsp_Rcerf_Reg
1196
Mcbsp_Xcere_Reg
1197
Mcbsp_Xcerf_Reg
1197
Mcbsp_Rcerg_Reg
1198
Mcbsp_Rcerh_Reg
1198
Mcbsp_Xcerg_Reg
1199
Mcbsp_Xcerh_Reg
1199
REV_REG Field Descriptions
1199
Mcbsp_Rintclr_Reg
1200
Mcbsp_Xintclr_Reg
1200
Mcbsp_Rovflclr_Reg
1200
Mcbsp_Sysconfig_Reg
1201
Mcbsp_Thrsh2_Reg
1202
Mcbsp_Thrsh1_Reg
1202
Mcbsp_Irqstatus_Reg
1203
Mcbsp_Irqstatus_Reg Field Descriptions
1204
Mcbsp_Irqenable_Reg
1205
Mcbsp_Irqenable_Reg Field Descriptions
1206
Mcbsp_Wakeupen_Reg
1207
Mcbsp_Xccr_Reg
1208
Mcbsp_Rccr_Reg
1209
Mcbsp_Xccr_Reg Field Descriptions
1209
Mcbsp_Xbuffstat_Reg
1210
Mcbsp_Xbuffstat_Reg Field Descriptions
1210
Mcbsp_Rbuffstat_Reg
1211
Mcbsp_Rbuffstat_Reg Field Descriptions
1211
Mcbsp_Status_Reg
1212
System Overview
1214
Mcspi Interface Pins
1215
SPI Full-Duplex Transmission
1216
SPI Half-Duplex Transmission (Receive-Only Slave)
1217
SPI Half-Duplex Transmission (Transmit-Only Slave)
1217
Phase and Polarity Combinations
1219
Full Duplex Single Transfer Format with PHA
1220
Full Duplex Single Transfer Format with PHA
1221
Continuous Transfers with SPIEN Maintained Active (Single-Data-Pin Interface Mode)
1226
Continuous Transfers with SPIEN Maintained Active (Dual-Data-Pin Interface Mode)
1226
Extended SPI Transfer with Start Bit PHA
1228
Chip-Select SPIEN Timing Controls
1229
Chip Select ↔ Clock Edge Delay Depending on Configuration
1229
CLKSPIO High/Low Time Computation
1231
Clock Granularity Examples
1231
FIFO Writes, Word Length Relationship
1232
Transmit/Receive Mode with no FIFO Used
1233
Transmit/Receive Mode with Only Receive FIFO Enabled
1233
Transmit/Receive Mode with Only Transmit FIFO Used
1234
Transmit/Receive Mode with both FIFO Direction Used
1234
Transmit-Only Mode with FIFO Used
1235
Receive-Only Mode with FIFO Used
1235
Buffer Almost Full Level (AFL)
1236
Buffer Almost Empty Level (AEL)
1237
Master Single Channel Initial Delay
1238
Example of SPI Slave with One Master and Multiple Slave Devices on Channel
1241
SPI Half-Duplex Transmission (Receive-Only Slave)
1243
SPI Half-Duplex Transmission (Transmit-Only Slave)
1244
SPI Registers
1251
Mcspi System Configuration Register (MCSPI_SYSCONFIG)
1252
Mcspi System Status Register (MCSPI_SYSSTATUS)
1253
Mcspi Interrupt Status Register (MCSPI_IRQSTATUS)
1254
Mcspi Interrupt Status Register (MCSPI_IRQSTATUS) Field Descriptions
1255
Mcspi Interrupt Enable Register (MCSPI_IRQENABLE)
1257
Mcspi Interrupt Enable Register (MCSPI_IRQENABLE) Field Descriptions
1258
Mcspi System Register (MCSPI_SYST)
1259
Mcspi System Register (MCSPI_SYST) Field Descriptions
1260
Mcspi Module Control Register (MCSPI_MODULCTRL)
1261
Mcspi Module Control Register(MCSPI_MODULCTRL) Field Descriptions
1262
Mcspi Channel (I) Configuration Register (MCSPI_CH(I)Conf) Field Descriptions
1263
Data Lines Configurations
1266
Mcspi Channel (I) Status Register (MCSPI_CH(I)Stat)
1267
Mcspi Channel (I) Control Register (MCSPI_CH(I)CTRL)
1268
Mcspi Channel (I) Transmit Register (MCSPI_TX(I))
1269
Mcspi Channel (I) Receive Register (MCSPI_RX(I))
1269
Mcspi Transfer Levels Register (MCSPI_XFERLEVEL)
1270
Pcie Subsystem (PCIESS) Block Diagram
1274
Pcie Transaction Layer Packets Supported
1276
Outbound Address Translation
1278
Application Registers
1279
Example Demonstrating the Mapping of Non-Contiguous Memories to a Single Region
1281
Address Space Zero Relationships
1283
Register Blocks that Make up the Pcie Configuration Registers
1284
PCIE Configuration Register (PCIE_CFG) Field Descriptions
1287
Pcie Test Pattern Control Register (PCIE_TEST_CTRL)
1288
RM_DEFAULT_RSTCTRL Register
1289
RM_DEFAULT_RSTCTRL Register Field Descriptions
1289
RM_DEFAULT_RSTST Register
1290
RM_DEFAULT_RSTST Register Field Descriptions
1290
CM_DEFAULT_PCI_CLKSTCTRL Register
1291
CM_DEFAULT_PCI_CLKSTCTRL Register Field Descriptions
1291
CM_DEFAULT_PCI_CLKCTRL Register
1292
CM_DEFAULT_PCI_CLKCTRL Register Field Descriptions
1292
PCIESS Interrupt Events
1293
Device Power Management States
1298
Transitions between Link States
1299
Link State Transition to L1 State
1300
Device Power States and Link Power States Relations
1300
Idle/Stand-By State Supported
1302
Relationships between Power States and Link States
1302
Encoded Debug Registers Contents and Their Relation to LTSSM States
1306
PID Register
1309
PID Register Field Descriptions
1309
CMD_STATUS Register
1310
CMD_STATUS Register Field Descriptions
1310
CFG_SETUP Register
1311
IOBASE Register
1311
IOBASE Register Field Descriptions
1311
TLPCFG Register
1312
RSTCMD Register
1312
TLPCFG Register Field Descriptions
1312
RSTCMD Register Field Descriptions
1312
PMCMD Register
1313
PMCFG Register
1313
PMCMD Register Field Descriptions
1313
PMCFG Register Field Descriptions
1313
ACT_STATUS Register
1314
OB_SIZE Register
1314
ACT_STATUS Register Field Descriptions
1314
OB_SIZE Register Field Descriptions
1314
DIAG_CTRL Register
1315
ENDIAN Register
1315
DIAG_CTRL Register Field Descriptions
1315
ENDIAN Register Field Descriptions
1315
PRIORITY Register
1316
PRIORITY Register Field Descriptions
1316
EOI Register Field Descriptions
1316
MSI_IRQ Register
1317
EP_IRQ_SET Register
1317
EP_IRQ_CLR Register
1318
EP_IRQ_STATUS Register
1318
EP_IRQ_STATUS Register Field Descriptions
1318
GPR0 Register
1319
GPR1 Register
1319
GPR2 Register
1319
GPR0 Register Field Descriptions
1319
GPR1 Register Field Descriptions
1319
GPR2 Register Field Descriptions
1319
GPR3 Register
1320
MSI0_STATUS_RAW Register
1320
MSI0_IRQ_STATUS Register
1320
GPR3 Register Field Descriptions
1320
MSI0_IRQ_STATUS Register Field Descriptions
1320
MSI0_IRQ_ENABLE_SET Register
1321
MSI0_IRQ_ENABLE_CLR Register
1321
IRQ_STATUS_RAW Register
1322
IRQ_STATUS Register
1322
IRQ_STATUS Register Field Descriptions
1322
IRQ_ENABLE_CLR Register
1323
IRQ_ENABLE_SET Register Field Descriptions
1323
ERR_IRQ_STATUS_RAW Register
1324
ERR_IRQ_STATUS Register
1324
ERR_IRQ_STATUS Register Field Descriptions
1324
ERR_IRQ_ENABLE_SET Register
1325
ERR_IRQ_ENABLE_CLR Register
1326
PMRST_IRQ_STATUS_RAW Register
1327
PMRST_IRQ_STATUS Register
1327
PMRST_IRQ_STATUS Register Field Descriptions
1327
PMRST_ENABLE_SET Register
1328
PMRST_ENABLE_CLR Register
1328
Ob_Offset_Indexn Register
1329
Ob_Offsetn_Hi Register
1329
Ob_Offset_Indexn Register Field Descriptions
1329
IB_BAR0 Register
1330
IB_BAR0 Register Field Descriptions
1330
IB_START0_LO Register
1331
IB_START0_HI Register
1331
IB_OFFSET0 Register
1332
IB_BAR1 Register
1332
IB_OFFSET0 Register Field Descriptions
1332
IB_BAR1 Register Field Descriptions
1332
IB_START1_LO Register
1333
IB_START1_HI Register
1333
IB_OFFSET1 Register
1334
IB_BAR2 Register
1334
IB_OFFSET 1 Register Field Descriptions
1334
IB_BAR2 Register Field Descriptions
1334
IB_START2_LO Register
1335
IB_START2_HI Register
1335
IB_OFFSET2 Register
1336
IB_BAR3 Register
1336
IB_OFFSET2 Register Field Descriptions
1336
IB_BAR3 Register Field Descriptions
1336
IB_START3_LO Register
1337
IB_START3_HI Register
1337
IB_OFFSET3 Register
1338
IB_OFFSET3 Register Field Descriptions
1338
PCS_CFG0 Register
1339
PCS_CFG0 Register Field Descriptions
1339
PCS_CFG1 Register
1340
PCS_STATUS Register
1340
PCS_STATUS Register Field Descriptions
1340
SERDES_CFG0 Register
1341
SERDES_CFG0 Register Field Descriptions
1341
SERDES_CFG1 Register
1342
SERDES_CFG1 Register Field Descriptions
1342
VENDOR_DEVICE_ID Register
1343
13.4.5 Configuration Registers Common to Type 0 and Type 1 Headers
1343
STATUS_COMMAND Register
1344
CLASSCODE_REVID Register
1345
CLASSCODE_REVID Register Field Descriptions
1345
BIST_HEADER Register
1346
13.4.6 Configuration Type 0 Registers
1346
BIST_HEADER Register Field Descriptions
1346
BAR0 Register
1347
BAR0 Register Field Descriptions
1347
BAR1 Register
1348
BAR1 Register Field Descriptions
1348
BAR2 Register
1349
BAR2 Register Field Descriptions
1349
BAR3 Register
1350
BAR3 Register Field Descriptions
1350
BAR4 Register
1351
BAR4 Register Field Descriptions
1351
BAR5 Register
1352
BAR5 Register Field Descriptions
1352
SUBSYS_VNDR_ID Register
1353
EXPNSN_ROM Register
1353
CAP_PTR Register
1354
INT_PIN Register
1354
13.4.7 Configuration Type 1 Registers
1355
BIST_HEADER Register Field Descriptions
1355
BAR0 Register
1356
BAR1 Register
1356
BAR0 Register Field Descriptions
1356
BAR1 Register Field Descriptions
1356
BAR1 Register
1357
BUSNUM Register
1357
BAR1 Register Field Descriptions
1357
BUSNUM Register Field Descriptions
1357
SECSTAT Register
1358
SECSTAT Register Field Descriptions
1358
MEMSPACE Register
1359
PREFETCH_MEM Register
1359
MEMSPACE Register Field Descriptions
1359
PREFETCH_BASE Register
1360
PREFETCH_LIMIT Register
1360
IOSPACE Register
1360
PREFETCH_BASE Field Descriptions
1360
PREFETCH_LIMIT Register Field Descriptions
1360
IOSPACE Register Field Descriptions
1360
CAP_PTR Register
1361
EXPNSN_ROM Register
1361
BRIDGE_INT Register
1362
PCIE_CAP Register
1363
13.4.8 Pcie Capability Registers
1363
DEVICE_CAP Register
1364
DEV_STAT_CTRL Register
1365
DEV_STAT_CTRL Register Field Descriptions
1365
LINK_CAP Register
1366
LINK_STAT_CTRL Register
1367
LINK_STAT_CTRL Register Field Descriptions
1367
SLOT_CAP Register
1368
SLOT_STAT_CTRL Register
1369
SLOT_STAT_CTRL Register Field Descriptions
1369
ROOT_CTRL_CAP Register
1370
ROOT_STATUS Register
1370
ROOT_STATUS Register Field Descriptions
1370
DEV_CAP2 Register
1371
DEV_STAT_CTRL2 Register
1371
DEV_CAP2 Register Field Descriptions
1371
DEV_STAT_CTRL2 Register Field Descriptions
1371
LINK_CTRL2 Register
1372
LINK_CTRL2 Register Field Descriptions
1372
PCIE_EXTCAP Register
1373
13.4.9 Pcie Extended Capability Registers
1373
PCIE_EXTCAP Register Field Descriptions
1373
PCIE_UNCERR Register
1374
PCIE_UNCERR Register Field Descriptions
1374
PCIE_UNCERR_MASK Register
1375
PCIE_UNCERR_MASK Register Field Descriptions
1375
PCIE_UNCERR_SVRTY Register
1376
PCIE_UNCERR_SVRTY Register Field Descriptions
1376
PCIE_CERR Register
1377
PCIE_CERR Register Field Descriptions
1377
PCIE_CERR_MASK Register
1378
PCIE_CERR_MASK Register Field Descriptions
1378
PCIE_ACCR Register
1379
HDR_LOG0 Register
1379
HDR_LOG1 Register
1379
PCIE_ACCR Register Field Descriptions
1379
HDR_LOG0 Register Field Descriptions
1379
HDR_LOG1 Register Field Descriptions
1379
HDR_LOG2 Register
1380
HDR_LOG3 Register
1380
RC_ERR_CMD Register
1380
HDR_LOG2 Register Field Descriptions
1380
HDR_LOG3 Register Field Descriptions
1380
RC_ERR_ST Register
1381
ERR_SRC_ID Register
1381
MSI_CAP Register
1382
13.4.10 Message Signaled Interrupts Registers
1382
MSI_LOW32 Register
1383
MSI_UP32 Register
1383
MSI_DATA Register
1383
MSI_LOW32 Register Field Descriptions
1383
MSI_UP32 Register Field Descriptions
1383
MSI_DATA Register Field Descriptions
1383
PMCAP Register
1384
13.4.11 Power Management Capability Registers
1384
PMCAP Register Field Descriptions
1384
PM_CTL_STAT Register
1385
PM_CTL-STAT Register Field Descriptions
1385
ACKTIMER Register
1386
OMSG Register
1386
13.4.12 Port Logic Registers
1386
ACKTIMER Register Field Descriptions
1386
OMSG Register Field Descriptions
1386
FORCE_LINK Register
1387
ACK_FREQ Register
1387
FORCE_LINK Register Field Descriptions
1387
LINK_CTRL Register
1388
LINK_CTRL Register Field Descriptions
1388
LANE_SKEW Register
1389
SYM_NUM Register
1389
LANE_SKEW Register Field Descriptions
1389
SYMTIMER_FLTMASK Register
1390
FLT_MASK2 Register
1391
DEBUG0 Register
1391
FLT_MASK2 Register Field Descriptions
1391
DEBUG0 Register Field Descriptions
1391
DEBUG1 Register
1392
DEBUG1 Register Field Descriptions
1392
GEN2 Register
1393
Functional and Interface Clocks
1397
Master Module Standby-Mode Settings
1398
Master Module Standby Status
1398
Module Idle Mode Settings
1398
Slave Module Idle Status
1399
Slave Module Mode Settings in PRCM
1399
Module Clock Enabling Condition
1399
Generic Clock Domain
1400
Clock Domain Functional Clock States
1400
Clock Domain State Transitions
1401
Clock Domain States
1401
Power Domain Block Diagram
1402
Clock Transition Mode Settings
1402
States of a Logic Area in a Power Domain
1403
States of a Memory Area in a Power Domain
1403
Power Domain Control and Status Registers
1403
Device Flying-Adder Plls
1405
14.3.1 Active Power Domain Modules Attribute
1406
14.3.2 Alwayson Power Domain Modules Attribute
1406
14.3.3 Default Power Domain Modules Attribute
1408
14.3.4 SGX Power Domain Modules Attribute
1408
External Clock Sources to PR
1409
14.4.3 Internal Clock Sources
1410
Main FAPLL Interface to PRCM
1411
MAIN PLL Dividers
1411
DDR FAPLL Interface to PRCM
1412
DDR PLL Dividers
1412
Video FAPLL Interface to PRCM
1413
Video PLL Dividers
1413
Audio FAPLL Interface to PRCM
1414
Timer Functional Clock Mux
1414
Audio PLL Dividers
1414
Mcasp and Mcbsp Clock Connections
1415
Timer Functional Mux Select
1415
Mcasp and Mcbsp Clock Mux Select
1415
Reset Sources Overview
1417
Voltage and Power Domains
1422
PRCM Module Summary
1424
PRCM Registers
1424
Reset Control (PRM_RSTCTRL) Register
1427
PRM_RSTTIME Register
1427
Reset Control (PRM_RSTCTRL) Register Field Descriptions
1427
PRM_RSTTIME Register Field Descriptions
1427
PRM_RSTST Register
1428
PRM_RSTST Register Field Descriptions
1428
CM_CLKOUT_CTRL Register
1429
CM_CLKOUT_CTRL Register Field Descriptions
1429
REVISION_PRM Register
1430
CM_SYSCLK1_CLKSEL Register
1431
CM_SYSCLK2_CLKSEL Register
1431
CM_SYSCLK1_CLKSEL Register Field Descriptions
1431
CM_SYSCLK2_CLKSEL Register Field Descriptions
1431
CM_SYSCLK4_CLKSEL Register
1432
CM_SYSCLK4_CLKSEL Register Field Descriptions
1432
CM_SYSCLK5_CLKSEL Register
1433
CM_SYSCLK6_CLKSEL Register
1433
CM_SYSCLK5_CLKSEL Register Field Descriptions
1433
CM_SYSCLK6_CLKSEL Register Field Descriptions
1433
CM_SYSCLK7_CLKSEL Register
1434
CM_SYSCLK10_CLKSEL Register
1434
CM_SYSCLK7_CLKSEL Register Field Descriptions
1434
CM_SYSCLK10_CLKSEL Register Field Descriptions
1434
CM_SYSCLK11_CLKSEL Register
1435
CM_SYSCLK13_CLKSEL Register
1435
CM_SYSCLK11_CLKSEL Register Field Descriptions
1435
CM_SYSCLK13_CLKSEL Register Field Descriptions
1435
CM_SYSCLK15_CLKSEL Register
1436
CM_VPB3_CLKSEL Register
1436
CM_SYSCLK15_CLKSEL Register Field Descriptions
1436
CM_VPB3_CLKSEL Register Field Descriptions
1436
CM_VPC1_CLKSEL Register
1437
CM_VPD1_CLKSEL Register
1437
CM_VPC1_CLKSEL Register Field Descriptions
1437
CM_VPD1_CLKSEL Register Field Descriptions
1437
CM_SYSCLK19_CLKSEL Register
1438
CM_SYSCLK20_CLKSEL Register
1438
CM_SYSCLK19_CLKSEL Register Field Descriptions
1438
CM_SYSCLK20_CLKSEL Register Field Descriptions
1438
CM_SYSCLK21_CLKSEL Register
1439
CM_SYSCLK22_CLKSEL Register
1439
CM_SYSCLK21_CLKSEL Register Field Descriptions
1439
CM_SYSCLK22_CLKSEL Register Field Descriptions
1439
CM_SYSCLK14_CLKSEL Register
1440
CM_SYSCLK16_CLKSEL Register
1440
CM_SYSCLK14_CLKSEL Register Field Descriptions
1440
CM_SYSCLK16_CLKSEL Register Field Descriptions
1440
CM_SYSCLK18_CLKSEL Register
1441
CM_AUDIOCLK_MCASP0_CLKSEL Register
1441
CM_SYSCLK18_CLKSEL Register Field Descriptions
1441
CM_AUDIOCLK_MCASP0_CLKSEL Register Field Descriptions
1441
CM_AUDIOCLK_MCASP1_CLKSEL Register
1442
CM_AUDIOCLK_MCASP2_CLKSEL Register
1442
CM_AUDIOCLK_MCASP1_CLKSEL Register Field Descriptions
1442
CM_AUDIOCLK_MCASP2_CLKSEL Register Field Descriptions
1442
CM_AUDIOCLK_MCBSP_CLKSEL Register
1443
CM_TIMER1_CLKSEL Register
1443
CM_AUDIOCLK_MCBSP_CLKSEL Register Field Descriptions
1443
CM_TIMER1_CLKSEL Register Field Descriptions
1443
CM_TIMER2_CLKSEL Register
1444
CM_TIMER3_CLKSEL Register
1444
CM_TIMER2_CLKSEL Register Field Descriptions
1444
CM_TIMER3_CLKSEL Register Field Descriptions
1444
CM_TIMER4_CLKSEL Register
1445
CM_TIMER5_CLKSEL Register
1445
CM_TIMER4_CLKSEL Register Field Descriptions
1445
CM_TIMER5_CLKSEL Register Field Descriptions
1445
CM_TIMER6_CLKSEL Register
1446
CM_SYSCLK23_CLKSEL Register
1446
CM_TIMER6_CLKSEL Register Field Descriptions
1446
CM_SYSCLK23_CLKSEL Register Field Descriptions
1446
CM_SYSCLK24_CLKSEL Register
1447
CM_SYSCLK24_CLKSEL Register Field Descriptions
1447
CM_GEM_CLKSTCTRL Register
1448
CM_GEM_CLKSTCTRL Register Field Descriptions
1448
CM_HDDSS_CLKSTCTRL Register
1449
CM_HDDSS_CLKSTCTRL Register Field Descriptions
1449
CM_ACTIVE_GEM_CLKCTRL Register
1451
CM_ACTIVE_GEM_CLKCTRL Register Field Descriptions
1451
CM_ACTIVE_HDDSS_CLKCTRL Register
1452
CM_ACTIVE_HDDSS_CLKCTRL Register Field Descriptions
1452
CM_DEFAULT_L3_MED_CLKSTCTRL Register
1453
CM_DEFAULT_L3_MED_CLKSTCTRL Register Field Descriptions
1453
CM_DEFAULT_L3_FAST_CLKSTCTRL Register
1454
CM_DEFAULT_L3_FAST_CLKSTCTRL Register Field Descriptions
1454
CM_DEFAULT_PCI_CLKSTCTRL Register
1455
CM_DEFAULT_PCI_CLKSTCTRL Register Field Descriptions
1455
CM_DEFAULT_L3_SLOW_CLKSTCTRL Register
1456
CM_DEFAULT_L3_SLOW_CLKSTCTRL Register Field Descriptions
1456
CM_DEFAULT_CLKSTCTRL Register
1457
CM_DEFAULT_CLKSTCTRL Register Field Descriptions
1457
CM_DEFAULT_EMIF_0_CLKCTRL Register
1458
CM_DEFAULT_EMIF_0_CLKCTRL Register Field Descriptions
1458
CM_DEFAULT_EMIF_1_CLKCTRL Register
1459
CM_DEFAULT_EMIF_1_CLKCTRL Register Field Descriptions
1459
CM_DEFAULT_DMM_CLKCTRL Register
1460
CM_DEFAULT_DMM_CLKCTRL Register Field Descriptions
1460
CM_DEFAULT_FW_CLKCTRL Register
1461
CM_DEFAULT_FW_CLKCTRL Register Field Descriptions
1461
CM_DEFAULT_USB_CLKCTRL Register
1462
CM_DEFAULT_USB_CLKCTRL Register Field Descriptions
1462
CM_DEFAULT_SATA_CLKCTRL Register
1463
CM_DEFAULT_SATA_CLKCTRL Register Field Descriptions
1463
CM_DEFAULT_CLKCTRL Register
1464
CM_DEFAULT_CLKCTRL Register Field Descriptions
1464
CM_DEFAULT_PCI_CLKCTRL Register
1465
CM_DEFAULT_PCI_CLKCTRL Register Field Descriptions
1465
CM_SGX_CLKSTCTRL Register
1466
CM_SGX_CLKSTCTRL Register Field Descriptions
1466
CM_SGX_SGX_CLKCTRL Register
1467
CM_SGX_SGX_CLKCTRL Register Field Descriptions
1467
PM_ACTIVE_PWRSTCTRL Register
1468
PM_ACTIVE_PWRSTCTRL Register Field Descriptions
1468
PM_ACTIVE_PWRSTST Register
1469
PM_ACTIVE_PWRSTST Register Field Descriptions
1469
RM_ACTIVE_RSTCTRL Register
1470
RM_ACTIVE_RSTST Register
1470
RM_ACTIVE_RSTCTRL Register Field Descriptions
1470
RM_ACTIVE_RSTST Register Field Descriptions
1470
PM_DEFAULT_PWRSTCTRL Register
1471
PM_DEFAULT_PWRSTCTRL Register Field Descriptions
1471
PM_DEFAULT_PWRSTST Register
1472
PM_DEFAULT_PWRSTST Register Field Descriptions
1472
RM_DEFAULT_RSTCTRL Register
1473
RM_DEFAULT_RSTCTRL Register Field Descriptions
1473
RM_DEFAULT_RSTST Register
1474
RM_DEFAULT_RSTST Register Field Descriptions
1474
PM_SGX_PWRSTCTRL Register
1475
RM_SGX_RSTCTRL Register
1475
PM_SGX_PWRSTCTRL Register Field Descriptions
1475
RM_SGX_RSTCTRL Register Field Descriptions
1475
PM_SGX_PWRSTST Register
1476
RM_SGX_RSTST Register
1476
PM_SGX_PWRSTST Register Field Descriptions
1476
RM_SGX_RSTST Register Field Descriptions
1476
CM_ALWON_L3_SLOW_CLKSTCTRL Register Field Descriptions
1477
CM_ETHERNET_CLKSTCTRL Register
1480
CM_ETHERNET_CLKSTCTRL Register Field Descriptions
1480
CM_ALWON_L3_MED_CLKSTCTRL Register
1481
CM_MMU_CLKSTCTRL Register
1481
CM_ALWON_L3_MED_CLKSTCTRL Register Field Descriptions
1481
CM_MMU_CLKSTCTRL Register Field Descriptions
1481
CM_MMUCFG_CLKSTCTRL Register
1482
CM_MMUCFG_CLKSTCTRL Register Field Descriptions
1482
CM_ALWON_OCMC_0_CLKSTCTRL Register
1483
CM_ALWON_OCMC_0_CLKSTCTRL Register Field Descriptions
1483
CM_ALWON_OCMC_1_CLKSTCTRL Register
1484
CM_ALWON_OCMC_1_CLKSTCTRL Register Field Descriptions
1484
CM_ALWON_MPU_CLKSTCTRL Register
1485
CM_ALWON_MPU_CLKSTCTRL Register Field Descriptions
1485
CM_ALWON_SYSCLK4_CLKSTCTRL Register
1486
CM_ALWON_SYSCLK4_CLKSTCTRL Register Field Descriptions
1486
CM_ALWON_SYSCLK5_CLKSTCTRL Register
1487
CM_ALWON_SYSCLK5_CLKSTCTRL Register Field Descriptions
1487
CM_ALWON_SYSCLK6_CLKSTCTRL Register
1488
CM_ALWON_SYSCLK6_CLKSTCTRL Register Field Descriptions
1488
CM_ALWON_RTC_CLKSTCTRL Register
1489
CM_ALWON_RTC_CLKSTCTRL Register Field Descriptions
1489
CM_ALWON_L3_FAST_CLKSTCTRL Register
1490
CM_ALWON_L3_FAST_CLKSTCTRL Register Field Descriptions
1490
CM_ALWON_MCASP0_CLKCTRL Register
1491
CM_ALWON_MCASP0_CLKCTRL Register Field Descriptions
1491
CM_ALWON_MCASP1_CLKCTRL Register
1492
CM_ALWON_MCASP1_CLKCTRL Register Field Descriptions
1492
CM_ALWON_MCASP2_CLKCTRL Register
1493
CM_ALWON_MCASP2_CLKCTRL Register Field Descriptions
1493
CM_ALWON_MCBSP_CLKCTRL Register
1494
CM_ALWON_MCBSP_CLKCTRL Register Field Descriptions
1494
CM_ALWON_UART_0_CLKCTRL Register
1495
CM_ALWON_UART_0_CLKCTRL Register Field Descriptions
1495
CM_ALWON_UART_1_CLKCTRL Register
1496
CM_ALWON_UART_1_CLKCTRL Register Field Descriptions
1496
CM_ALWON_UART_2_CLKCTRL Register
1497
CM_ALWON_UART_2_CLKCTRL Register Field Descriptions
1497
CM_ALWON_GPIO_0_CLKCTRL Register
1498
CM_ALWON_GPIO_0_CLKCTRL Register Field Descriptions
1498
CM_ALWON_GPIO_1_CLKCTRL Register
1499
CM_ALWON_GPIO_1_CLKCTRL Register Field Descriptions
1499
CM_ALWON_I2C_0_CLKCTRL Register
1500
CM_ALWON_I2C_0_CLKCTRL Register Descriptions
1500
CM_ALWON_I2C_1_CLKCTRL Register
1501
CM_ALWON_I2C_1_CLKCTRL Register Descriptions
1501
CM_ALWON_TIMER_1_CLKCTRL Register
1502
CM_ALWON_TIMER_1_CLKCTRL Register Descriptions
1502
CM_ALWON_TIMER_2_CLKCTRL Register
1503
CM_ALWON_TIMER_2_CLKCTRL Register Descriptions
1503
CM_ALWON_TIMER_3_CLKCTRL Register
1504
CM_ALWON_TIMER_3_CLKCTRL Register Descriptions
1504
CM_ALWON_TIMER_4_CLKCTRL Register
1505
CM_ALWON_TIMER_4_CLKCTRL Register Descriptions
1505
CM_ALWON_TIMER_5_CLKCTRL Register
1506
CM_ALWON_TIMER_5_CLKCTRL Register Descriptions
1506
CM_ALWON_TIMER_6_CLKCTRL Register
1507
CM_ALWON_TIMER_6_CLKCTRL Register Descriptions
1507
CM_ALWON_TIMER_7_CLKCTRL Register
1508
CM_ALWON_TIMER_7_CLKCTRL Register Descriptions
1508
CM_ALWON_WDTIMER_CLKCTRL Register
1509
CM_ALWON_WDTIMER_CLKCTRL Register Descriptions
1509
CM_ALWON_SPI_CLKCTRL Register
1510
CM_ALWON_SPI_CLKCTRL Register Descriptions
1510
CM_ALWON_MAILBOX_CLKCTRL Register
1511
CM_ALWON_MAILBOX_CLKCTRL Register Descriptions
1511
CM_ALWON_SPINBOX_CLKCTRL Register
1512
CM_ALWON_SPINBOX_CLKCTRL Register Descriptions
1512
CM_ALWON_MMUDATA_CLKCTRL Register
1513
CM_ALWON_MMUDATA_CLKCTRL Register Descriptions
1513
CM_ALWON_MMUCFG_CLKCTRL Register
1514
CM_ALWON_MMUCFG_CLKCTRL Register Descriptions
1514
CM_ALWON_SDIO_CLKCTRL Register
1515
CM_ALWON_SDIO_CLKCTRL Register Descriptions
1515
CM_ALWON_OCMC_0_CLKCTRL Register
1516
CM_ALWON_OCMC_0_CLKCTRL Register Descriptions
1516
CM_ALWON_OCMC_1_CLKCTRL Register
1517
CM_ALWON_OCMC_1_CLKCTRL Register Descriptions
1517
CM_ALWON_CONTRL_CLKCTRL Register
1518
CM_ALWON_CONTRL_CLKCTRL Register Descriptions
1518
CM_ALWON_GPMC_CLKCTRL Register
1519
CM_ALWON_GPMC_CLKCTRL Register Descriptions
1519
CM_ALWON_ETHERNET_0_CLKCTRL Register
1520
CM_ALWON_ETHERNET_0_CLKCTRL Register Descriptions
1520
CM_ALWON_ETHERNET_1_CLKCTRL Register
1521
CM_ALWON_ETHERNET_1_CLKCTRL Register Descriptions
1521
CM_ALWON_MPU_CLKCTRL Register
1522
CM_ALWON_MPU_CLKCTRL Register Descriptions
1522
CM_ALWON_L3_CLKCTRL Register
1523
CM_ALWON_L3_CLKCTRL Register Descriptions
1523
CM_ALWON_L4HS_CLKCTRL Register
1524
CM_ALWON_L4HS_CLKCTRL Register Descriptions
1524
CM_ALWON_L4LS_CLKCTRL Register
1525
CM_ALWON_L4LS_CLKCTRL Register Descriptions
1525
CM_ALWON_RTC_CLKCTRL Register
1526
CM_ALWON_RTC_CLKCTRL Register Descriptions
1526
CM_ALWON_TPCC_CLKCTRL Register
1527
CM_ALWON_TPCC_CLKCTRL Register Descriptions
1527
CM_ALWON_TPTC0_CLKCTRL Register
1528
CM_ALWON_TPTC0_CLKCTRL Register Descriptions
1528
CM_ALWON_TPTC1_CLKCTRL Register
1529
CM_ALWON_TPTC1_CLKCTRL Register Descriptions
1529
CM_ALWON_TPTC2_CLKCTRL Register
1530
CM_ALWON_TPTC2_CLKCTRL Register Descriptions
1530
CM_ALWON_TPTC3_CLKCTRL Register
1531
CM_ALWON_TPTC3_CLKCTRL Register Descriptions
1531
CM_ALWON_SR_0_CLKCTRL Register
1532
CM_ALWON_SR_0_CLKCTRL Register Descriptions
1532
CM_ALWON_SR_1_CLKCTRL Register
1533
CM_ALWON_SR_1_CLKCTRL Register Descriptions
1533
RTC Block Diagram
1536
RTC Functional Block Diagram
1537
RTC Signals
1537
Interrupt Trigger Events
1538
Kick Register State Machine Diagram
1539
RTC Register Names and Values
1540
Flow Control for Updating RTC Registers
1541
Compensation Illustration
1542
Real-Time Clock (RTC) Registers
1544
Seconds Register (SECONDS_REG)
1545
Minutes Register (MINUTES_REG)
1545
Hours Register (HOURS_REG)
1546
Day of the Month (DAYS_REG) Field Descriptions
1546
Month Register (MONTHS_REG)
1547
Year Register (YEARS_REG)
1547
Alarm Second Register (ALARM_SECONDS_REG)
1548
Day of the Week (WEEKS_REG) Field Descriptions
1548
Alarm Minute Register (ALARM_MINUTES_REG)
1549
Alarm Hour Register (ALARM_HOURS_REG)
1549
Alarm Month Register (ALARM_MONTHS_REG)
1550
Alarm Day of the Month Register (ALARM_DAYS_REG) Field Descriptions
1550
Alarm Year Register (ALARM_YEARS_REG)
1551
Control Register (CTRL_REG) Field Descriptions
1552
Status Register (STATUS_REG) Field Descriptions
1554
Interrupt Register (INTERRUPTS_REG) Field Descriptions
1555
Compensation (LSB) Register (COMP_LSB_REG) Field Descriptions
1556
Compensation (MSB) Register (COMP_MSB_REG) Field Descriptions
1557
Oscillator Register (OSC_REG)
1558
Scratch Registers (Scratchx_Reg) Field Descriptions
1558
Kick0 Register (KICK0R)
1559
Kick1 Register (KICK1R)
1559
Kick0 Register (KICK0R) Field Descriptions
1559
Kick1 Register (KICK1R) Field Descriptions
1559
RTC Revision Register (RTC_REVISION)
1560
System Configuration Register (RTC_SYSCONFIG) Field Descriptions
1560
Wakeup Enable Register (RTC_IRQWAKEEN)
1561
SATA Core Block Diagram
1566
MPY Bit Field of P0PHYCR
1568
SATA Interface Signal Descriptions
1569
SATA Controller Registers
1592
HBA Capabilities Register (CAP)
1594
HBA Capabilities Register (CAP) Field Descriptions
1594
Global HBA Control Register (GHC)
1595
Global HBA Control Register (GHC) Field Descriptions
1595
Interrupt Status Register (IS)
1596
Interrupt Status Register (IS) Field Descriptions
1596
Ports Implemented Register (PI)
1597
AHCI Version Register (VS)
1597
Ports Implemented Register (PI) Field Descriptions
1597
AHCI Version Register (VS) Field Descriptions
1597
Command Completion Coalescing Control Register (CCC_CTL)
1598
Command Completion Coalescing Ports Register (CCC_PORTS)
1599
BIST Active FIS Register (BISTAFR)
1600
BIST Active FIS Register (BISTAFR) Field Descriptions
1600
BIST Control Register (BISTCR)
1601
BIST Control Register (BISTCR) Field Descriptions
1601
BIST FIS Count Register (BISTFCTR)
1603
BIST Status Register (BISTSR)
1603
BIST FIS Count Register (BISTFCTR) Field Description
1603
BIST Status Register (BISTSR) Field Description
1603
BIST DWORD Error Count Register (BISTDECR)
1604
BIST DWORD Error Count Register (TIMER1MS)
1604
BIST DWORD Error Count Register (BISTDECR) Field Description
1604
BIST DWORD Error Count Register (TIMER1MS) Field Description
1604
Global Parameter 1 Register (GPARAM1R)
1605
Global Parameter 1 Register (GPARAM1R) Field Descriptions
1605
Global Parameter 2 Register (GPARAM2R)
1606
Global Parameter 2 Register (GPARAM2R) Field Descriptions
1606
Port Parameter Register (PPARAMR)
1607
Port Parameter Register (PPARAMR) Field Descriptions
1607
Test Register (TESTR)
1608
Test Register (TESTR) Field Descriptions
1608
Version Register (VERSIONR)
1609
ID Register (IDR)
1609
Version Register (VERSIONR) Field Description
1609
ID Register (IDR) Field Description
1609
Port Command List Base Address Register (P#CLB)
1610
Port FIS Base Address Register (P#FB)
1610
Port Command List Base Address Register (P#CLB) Field Description
1610
Port FIS Base Address Register (P#FB) Field Description
1610
Port Interrupt Status Register (P#IS)
1611
Port Interrupt Status Register (P#IS) Field Descriptions
1611
Port Interrupt Enable Register (P#IE)
1613
Port Interrupt Enable Register (P#IE) Field Descriptions
1613
Port Command Register (P#CMD)
1614
Port Command Register (P#CMD) Field Descriptions
1614
Port Task File Data Register (P#TFD)
1617
Port Signature Register (P#SIG)
1617
Port Task File Data Register (P#TFD) Field Descriptions
1617
Port Signature Register (P#SIG) Field Description
1617
Port Serial ATA Status Register (P#SSTS)
1618
Port Serial ATA Status Register (P#SSTS) Field Descriptions
1618
Port Serial ATA Control Register (P#SCTL)
1619
Port Serial ATA Control Register (P#SCTL) Field Descriptions
1619
Port Serial ATA Error Register (P#SERR)
1620
Port Serial ATA Error Register (P#SERR) Field Descriptions
1620
Port Serial ATA Active Register (P#SACT)
1622
Port Command Issue Register (P#CI)
1622
Port Serial ATA Active Register (P#SACT) Field Description
1622
Port Command Issue Register (P#CI) Field Description
1622
Port Serial ATA Notification Register (P#SNTF)
1623
Port Serial ATA Notification Register (P#SNTF) Field Description
1623
Port DMA Control Register (P#DMACR)
1624
Port DMA Control Register (P#DMACR) Field Description
1624
Port PHY Control Register (P#PHYCR)
1626
Port PHY Control Register (P#PHYCR) Field Descriptions
1626
Port PHY Status Register (P#PHYSR)
1630
Port PHY Status Register (P#PHYSR) Field Description
1630
Idle Register (IDLE)
1631
Idle Register (IDLE) Field Description
1631
PHY Configuration Register 2 (PHYCFGR2)
1632
PHY Configuration Register 2 (PHYCFGR2) Field Description
1632
Timer Resolution and Maximum Range
1634
Timer Block Diagram
1635
TCRR Timing Value
1636
Capture Wave Example for CAPT_MODE
1637
Prescaler Functionality
1638
Timing Diagram of Pulse-Width Modulation with SCPWM
1639
Prescaler Clock Ratios Value
1640
Value and Corresponding Interrupt Period
1640
OCP Error Reporting
1641
Timer Registers
1644
Identification Register (TIDR) Register
1645
Identification Register (TIDR) Field Descriptions
1645
Timer OCP Configuration Register (TIOCP_CFG)
1646
Timer IRQ EOI Register (IRQ_EOI)
1647
Timer IRQSTATUS Raw Register (IRQSTATUS_RAW)
1648
Timer IRQSTATUS Register (IRQSTATUS)
1649
Timer IRQSTATUS Register (IRQSTATUS) Field Descriptions
1649
Timer IRQENABLE Set Register (IRQENABLE_SET) Field Descriptions
1650
Timer IRQENABLE Clear Register (IRQENABLE_CLR)
1651
Timer IRQ Wakeup Enable Register (IRQWAKEEN)
1652
Timer Control Register (TCLR)
1652
Timer IRQ Wakeup Enable Register (IRQWAKEEN) Field Descriptions
1652
Timer Control Register (TCLR) Field Descriptions
1653
Timer Counter Register (TCRR)
1654
Timer Load Register (TLDR)
1654
Timer Counter Register (TCRR) Field Descriptions
1654
Timer Load Register (TLDR) Field Descriptions
1654
Timer Trigger Register (TTGR)
1655
Timer Write Posted Status Register (TWPS)
1655
Timer Trigger Register (TTGR) Field Descriptions
1655
Timer Write Posted Status Register (TWPS) Field Descriptions
1655
Timer Match Register (TMAR)
1656
Timer Capture Register (TCAR1)
1656
Timer Match Register (TMAR) Field Descriptions
1656
Timer Capture Register (TCAR1) Field Descriptions
1656
Timer Synchronous Interface Control Register (TSICR)
1657
Timer Capture Register (TCAR2)
1657
Timer Synchronous Interface Control Register (TSICR) Field Descriptions
1657
Timer Capture Register (TCAR2) Field Descriptions
1657
Watchdog Timer Block Diagram
1660
Watchdog Timer Events
1661
Watchdog Timers General Functional View
1662
Count and Prescaler Default Reset Values
1662
Prescaler Clock Ratio Values
1663
Reset Period Examples
1663
Default Watchdog Timer Reset Periods
1664
Global Initialization of Surrounding Modules
1667
Watchdog Timer Module Global Initialization
1667
Watchdog Timer Basic Configuration
1667
Disable the Watchdog Timer
1668
Enable the Watchdog Timer
1668
Watchdog Timer Registers
1668
WDT_WIDR Register
1669
WDT_WDSC Register
1669
WDT_WIDR Register Field Descriptions
1669
WDT_WDSC Register Field Descriptions
1669
WDT_WDST Register
1670
WDT_WISR Register
1670
WDT_WDST Register Field Descriptions
1670
WDT_WISR Register Field Descriptions
1670
WDT_WIER Register
1671
WDT_WCLR Register
1671
WDT_WIER Register Field Descriptions
1671
WDT_WCLR Register Field Descriptions
1671
WDT_WCRR Register
1672
WDT_WLDR Register
1672
WDT_WTGR Register
1672
WDT_WCRR Register Field Descriptions
1672
WDT_WLDR Register Field Descriptions
1672
WDT_WTGR Register Field Descriptions
1672
WDT_WWPS Register
1673
WDT_WWPS Register Field Descriptions
1673
Wdt_Wdly
1674
WDT_WSPR Register
1674
WDT_WDLY Register Field Descriptions
1674
WDT_WSPR Register Field Descriptions
1674
WDT_WIRQSTATRAW Register
1675
WDT_WIRQSTATRAW Register Field Descriptions
1675
WIRQSTAT Register
1676
WDT_WIRQSTAT Registerfield Descriptions
1676
WDT_WIRQENSET Register
1677
WDT_WIRQENSET Register Field Descriptions
1677
WDT_WIRQENCLR Register
1678
WDT_WIRQENCLR Register Field Descriptions
1678
UART Signal Description
1682
UART Mode Selection
1682
UART to UART Connection with Full Handshaking
1683
UART Frame Data Format
1683
UART Irda to External IR Device
1687
Irda SIR Frame Format
1688
Irda SIR Encoding Mechanism
1689
Irda SIR Decoding Mechanism
1689
SIR Free Format Mode
1690
MIR Transmit Frame Format
1692
MIR Baud Rate Adjustment Mechanism
1693
Serial Infrared Interaction Pulse (SIP)
1693
FIR Transmit Frame Format
1695
RC-5 Bit Encoding
1696
SIRC Bit Encoding
1696
SIRC Packet Format
1697
SIRC Bit Transmission Example
1697
CIR Pulse Modulation
1698
CIR Modulation Duty Cycle
1699
FIFO Management
1700
Receive FIFO Interrupt Request Generation
1701
Transmit FIFO Interrupt Request Generation
1701
Receive FIFO DMA Request Generation (32 Characters)
1703
Transmit FIFO DMA Request Generation (56 Spaces)
1703
Transmit FIFO DMA Request Generation (8 Spaces)
1704
Transmit FIFO DMA Request Generation (1 Space)
1704
Transmission Process
1705
Reception Process
1705
UART Mode Interrupts
1707
Irda Mode Interrupts
1708
CIR Mode Interrupts
1708
BAUD Rate Generator
1710
UART Baud Rate Settings (48-Mhz Clock)
1711
Irda Baud Rates Settings
1711
UART Registers
1713
Receiver Holding Register (RHR)
1714
Transmit Holding Register (THR)
1714
Receiver Holding Register (RHR) Field Descriptions
1714
Transmit Holding Register (THR) Field Descriptions
1714
UART Interrupt Enable Register (IER)
1715
UART Interrupt Enable Register (IER) Field Descriptions
1715
Irda Interrupt Enable Register (IER)
1716
Irda Interrupt Enable Register (IER) Field Descriptions
1716
CIR Interrupt Enable Register (IER)
1717
CIR Interrupt Enable Register (IER) Field Descriptions
1717
UART Interrupt Identification Register (IIR)
1718
UART Interrupt Identification Register (IIR) Field Descriptions
1718
Irda Interrupt Identification Register (IIR)
1719
Irda Interrupt Identification Register (IIR) Field Descriptions
1719
CIR Interrupt Identification Register (IIR)
1720
CIR Interrupt Identification Register (IIR) Field Descriptions
1720
FIFO Control Register (FCR) Field Descriptions
1721
Line Control Register (LCR)
1722
Line Control Register (LCR) Field Descriptions
1722
Modem Control Register (MCR)
1723
Modem Control Register (MCR) Field Descriptions
1723
UART Line Status Register (LSR)
1724
UART Line Status Register (LSR) Field Descriptions
1724
Irda Line Status Register (LSR)
1725
Irda Line Status Register (LSR) Field Descriptions
1725
CIR Line Status Register (LSR)
1726
CIR Line Status Register (LSR) Field Descriptions
1726
Modem Status Register (MSR)
1727
Modem Status Register (MSR) Field Descriptions
1727
Transmission Control Register (TCR)
1728
Scratchpad Register (SPR)
1728
Transmission Control Register (TCR) Field Descriptions
1728
Scratchpad Register (SPR) Field Descriptions
1728
Trigger Level Register (TLR)
1729
Trigger Level Register (TLR) Field Descriptions
1729
RX FIFO Trigger Level Setting Summary
1729
TX FIFO Trigger Level Setting Summary
1729
Mode Definition Register 1 (MDR1)
1730
Mode Definition Register 1 (MDR1) Field Descriptions
1730
Mode Definition Register 2 (MDR2)
1731
Mode Definition Register 2 (MDR2) Field Descriptions
1731
Status FIFO Line Status Register (SFLSR)
1732
RESUME Register
1732
Status FIFO Line Status Register (SFLSR) Field Descriptions
1732
RESUME Register Field Descriptions
1732
Status FIFO Register Low (SFREGL)
1733
Status FIFO Register High (SFREGH)
1733
Status FIFO Register Low (SFREGL) Field Descriptions
1733
Status FIFO Register High (SFREGH) Field Descriptions
1733
BOF Control Register (BLR)
1734
BOF Control Register (BLR) Field Descriptions
1734
Auxiliary Control Register (ACREG)
1735
Auxiliary Control Register (ACREG) Field Descriptions
1735
Supplementary Control Register (SCR)
1736
Supplementary Control Register (SCR) Field Descriptions
1736
Supplementary Status Register (SSR)
1737
Supplementary Status Register (SSR) Field Descriptions
1737
BOF Length Register (EBLR)
1738
BOF Length Register (EBLR) Field Descriptions
1738
Module Version Register (MVR)
1739
Module Version Register (MVR) Field Descriptions
1739
System Configuration Register (SYSC)
1740
System Status Register (SYSS)
1740
System Configuration Register (SYSC) Field Descriptions
1740
System Status Register (SYSS) Field Descriptions
1740
Wake-Up Enable Register (WER)
1741
Wake-Up Enable Register (WER) Field Descriptions
1741
Carrier Frequency Prescaler Register (CFPS)
1742
Carrier Frequency Prescaler Register (CFPS) Field Descriptions
1742
Divisor Latches Low Register (DLL)
1743
Divisor Latches High Register (DLH)
1743
Divisor Latches Low Register (DLL) Field Descriptions
1743
Divisor Latches High Register (DLH) Field Descriptions
1743
Enhanced Feature Register (EFR)
1744
Enhanced Feature Register (EFR) Field Descriptions
1744
XON1/ADDR1 Register
1745
XON2/ADDR2 Register
1745
EFR[3:0] Software Flow Control Options
1745
XON1/ADDR1 Register Field Descriptions
1745
XON2/ADDR2 Register Field Descriptions
1745
XOFF1 Register
1746
XOFF2 Register
1746
XOFF1 Register Field Descriptions
1746
XOFF2 Register Field Descriptions
1746
Transmit Frame Length Low Register (TXFLL)
1747
Transmit Frame Length High Register (TXFLH)
1747
Transmit Frame Length Low Register (TXFLL) Field Descriptions
1747
Transmit Frame Length High Register (TXFLH) Field Descriptions
1747
Received Frame Length Low Register (RXFLL)
1748
Received Frame Length High Register (RXFLH)
1748
Received Frame Length Low Register (RXFLL) Field Descriptions
1748
Received Frame Length High Register (RXFLH) Field Descriptions
1748
UART Autobauding Status Register (UASR)
1749
UART Autobauding Status Register (UASR) Field Descriptions
1749
USB Subsystem Block Diagram
1754
USBSS Interface Signals
1756
CPU Actions at Transfer Phases
1763
Sequence of Transfer
1764
Flow Chart of Setup Stage of a Control Transfer in Peripheral Mode
1766
Flow Chart of Transmit Data Stage of a Control Transfer in Peripheral Mode
1767
Flow Chart of Receive Data Stage of a Control Transfer in Peripheral Mode
1768
PERI_TXCSR Register Bit Configuration for Bulk in Transactions
1770
PERI_RXCSR Register Bit Configuration for Bulk out Transactions
1772
PERI_TXCSR Register Bit Configuration for Isochronous in Transactions
1774
PERI_RXCSR Register Bit Configuration for Isochronous out Transactions
1775
Isochronous out Error Handling: Peripheral Mode
1776
Flow Chart of Setup Stage of a Control Transfer in Host Mode
1779
Flow Chart of Data Stage (in Data Phase) of a Control Transfer in Host Mode
1781
Flow Chart of Data Stage (out Data Phase) of a Control Transfer in Host Mode
1783
Flow Chart of Status Stage of Zero Data Request or Write Request of a Control Transfer in Host Mode
1785
Chart of Status Stage of a Read Request of a Control Transfer in Host Mode
1787
Packet Descriptor Layout
1797
Packet Descriptor Word 0 (PD0) Bit Field Descriptions
1797
Packet Descriptor Word 1 (PD1) Bit Field Descriptions
1798
Packet Descriptor Word 2 (PD2) Bit Field Descriptions
1798
Packet Descriptor Word 3 (PD3) Bit Field Descriptions
1798
Packet Descriptor Word 4 (PD4) Bit Field Descriptions
1799
Packet Descriptor Word 5 (PD5) Bit Field Descriptions
1799
Packet Descriptor Word 6 (PD6) Bit Field Descriptions
1799
Packet Descriptor Word 7 (PD7) Bit Field Descriptions
1799
Buffer Descriptor (BD) Layout
1800
Buffer Descriptor Word 0 (BD0) Bit Field Descriptions
1800
Buffer Descriptor Word 1 (BD1) Bit Field Descriptions
1800
Buffer Descriptor Word 2 (BD2) Bit Field Descriptions
1800
Buffer Descriptor Word 3 (BD3) Bit Field Descriptions
1800
Buffer Descriptor Word 4 (BD4) Bit Field Descriptions
1800
Buffer Descriptor Word 5 (BD5) Bit Field Descriptions
1801
Buffer Descriptor Word 6 (BD6) Bit Field Descriptions
1801
Buffer Descriptor Word 7 (BD7) Bit Field Descriptions
1801
Teardown Descriptor Layout
1802
Teardown Descriptor Word 0 Bit Field Descriptions
1802
Teardown Descriptor Words 1 to 7 Bit Field Descriptions
1802
Queue-Endpoint Assignments
1803
High-Level Transmit and Receive Data Transfer Example
1812
Transmit Descriptors and Queue Status Configuration
1814
Transmit USB Data Flow Example (Initialization)
1815
Receive Buffer Descriptors and Queue Status Configuration
1817
Receive USB Data Flow Example (Initialization)
1818
Bytes Test Packet Content
1819
Functional Representation of Interrupts
1821
Subsystem Interrupts
1822
CPPI DMA Packet Completion Hardware Interrupt Groupings
1822
Controller Interrupts
1824
USBSS Submodule Base Addresses and Size
1827
20.9.1 USBSS Registers
1827
USBSS Revision Register (REVREG)
1828
USBSS Revision Register (REVREG) Field Description
1828
USBSS SYSCONFIG Register (SYSCONFIG)
1829
USBSS SYSCONFIG Register (SYSCONFIG) Field Descriptions
1829
USBSS End of Interrupt Register (EOI)
1831
USBSS End of Interrupt Register (EOI) Field Descriptions
1831
Usbss Irq_Status_Raw (Irqstatraw)
1832
USBSS IRQ_STATUS_RAW (IRQSTATRAW) Field Descriptions
1832
Usbss Irq_Status (Irqstat)
1833
USBSS IRQ_STATUS (IRQSTAT) Field Descriptions
1833
USBSS IRQ_ENABLE_SET Register (IRQENABLER)
1834
USBSS IRQ_ENABLE_SET Register (IRQENABLER) Field Descriptions
1834
USBSS IRQ_ENABLE_CLR Register (IRQCLEARR)
1835
USBSS IRQ_ENABLE_CLR Register (IRQCLEARR) Field Descriptions
1835
USBSS IRQ_DMA_THRESHOLD_TX0_0 Register (IRQDMATHOLDTX00)
1836
USBSS IRQ_DMA_THRESHOLD_TX0_0 Register (IRQDMATHOLDTX00) Field Descriptions
1836
USBSS IRQ_DMA_THRESHOLD_TX0_1 Register (IRQDMATHOLDTX01)
1837
USBSS IRQ_DMA_THRESHOLD_TX0_2 Register (IRQDMATHOLDTX02)
1837
USBSS IRQ_DMA_THRESHOLD_TX0_1 Register (IRQDMATHOLDTX01) Field Descriptions
1837
USBSS IRQ_DMA_THRESHOLD_TX0_2 Register (IRQDMATHOLDTX02) Field Descriptions
1837
USBSS IRQ_DMA_THRESHOLD_TX0_3 Register (IRQDMATHOLDTX03)
1838
USBSS IRQ_DMA_THRESHOLD_RX0_0 Register (IRQDMATHOLDRX00)
1838
USBSS IRQ_DMA_THRESHOLD_TX0_3 Register (IRQDMATHOLDTX03) Field Descriptions
1838
USBSS IRQ_DMA_THRESHOLD_RX0_0 Register (IRQDMATHOLDRX00) Field Descriptions
1838
USBSS IRQ_DMA_THRESHOLD_RX0_1 Register (IRQDMATHOLDRX01)
1839
USBSS IRQ_DMA_THRESHOLD_RX0_2 Register (IRQDMATHOLDRX02)
1839
USBSS IRQ_DMA_THRESHOLD_RX0_1 Register (IRQDMATHOLDRX00) Field Descriptions
1839
USBSS IRQ_DMA_THRESHOLD_RX0_2 Register (IRQDMATHOLDRX02) Field Descriptions
1839
USBSS IRQ_DMA_THRESHOLD_RX0_3 Register (IRQDMATHOLDRX03)
1840
USBSS IRQ_DMA_THRESHOLD_TX1_0 Register (IRQDMATHOLDTX10)
1840
USBSS IRQ_DMA_THRESHOLD_RX0_3 Register (IRQDMATHOLDRX03) Field Descriptions
1840
USBSS IRQ_DMA_THRESHOLD_TX1_0 Register (IRQDMATHOLDTX10) Field Descriptions
1840
USBSS IRQ_DMA_THRESHOLD_TX1_1 Register (IRQDMATHOLDTX11)
1841
USBSS IRQ_DMA_THRESHOLD_TX1_2 Register (IRQDMATHOLDTX12)
1841
USBSS IRQ_DMA_THRESHOLD_TX1_1 Register (IRQDMATHOLDTX11) Field Descriptions
1841
USBSS IRQ_DMA_THRESHOLD_TX1_2 Register (IRQDMATHOLDTX12) Field Descriptions
1841
USBSS IRQ_DMA_THRESHOLD_TX1_3 Register (IRQDMATHOLDTX13)
1842
USBSS IRQ_DMA_THRESHOLD_RX1_0 Register (IRQDMATHOLDRX10)
1842
USBSS IRQ_DMA_THRESHOLD_TX1_3 Register (IRQDMATHOLDTX13) Field Descriptions
1842
USBSS IRQ_DMA_THRESHOLD_RX1_0 Register (IRQDMATHOLDRX10) Field Descriptions
1842
USBSS IRQ_DMA_THRESHOLD_RX1_1 Register (IRQDMATHOLDRX11)
1843
USBSS IRQ_DMA_THRESHOLD_RX1_2 Register (IRQDMATHOLDRX12)
1843
USBSS IRQ_DMA_THRESHOLD_RX1_1 Register (IRQDMATHOLDRX11) Field Descriptions
1843
USBSS IRQ_DMA_THRESHOLD_RX1_2 Register (IRQDMATHOLDRX12) Field Descriptions
1843
USBSS IRQ_DMA_THRESHOLD_RX1_3 Register (IRQDMATHOLDRX13)
1844
USBSS IRQ_DMA_THRESHOLD_RX1_3 Register (IRQDMATHOLDRX13) Field Descriptions
1844
USBSS IRQ_DMA_ENABLE_0 Register (IRQDMAENABLE0)
1845
USBSS IRQ_DMA_ENABLE_0 Register (IRQDMAENABLE0) Field Descriptions
1845
USBSS IRQ_DMA_ENABLE_1 Register (IRQDMAENABLE1)
1846
USBSS IRQ_DMA_ENABLE_1 Register (IRQDMAENABLE1) Field Descriptions
1846
USBSS IRQ_FRAME_THRESHOLD_TX0_0 Register (IRQFRAMETHOLD00)
1847
USBSS IRQ_FRAME_THRESHOLD_TX0_1 Register (IRQFRAMETHOLD01)
1847
USBSS IRQ_FRAME_THRESHOLD_TX0_0 Register (IRQFRAMETHOLD00) Field Descriptions
1847
USBSS IRQ_FRAME_THRESHOLD_TX0_1 Register (IRQFRAMETHOLDTX01) Field Descriptions
1847
USBSS IRQ_FRAME_THRESHOLD_TX0_2 Register (IRQFRAMETHOLD02)
1848
USBSS IRQ_FRAME_THRESHOLD_TX0_3 Register (IRQFRAMETHOLD03)
1848
USBSS IRQ_FRAME_THRESHOLD_TX0_2 Register (IRQFRAMETHOLDTX02) Field Descriptions
1848
USBSS IRQ_FRAME_THRESHOLD_TX0_3 Register (IRQFRAMETHOLDTX03) Field Descriptions
1848
USBSS IRQ_FRAME_THRESHOLD_RX0_0 Register (IRQFRAMETHOLDRX00)
1849
USBSS IRQ_FRAME_THRESHOLD_RX0_1 Register (IRQFRAMETHOLDRX01)
1849
USBSS IRQ_FRAME_THRESHOLD_RX0_0 Register (IRQFRAMETHOLDRX00) Field Descriptions
1849
USBSS IRQ_FRAME_THRESHOLD_RX0_1 Register (IRQFRAMETHOLDRX01) Field Descriptions
1849
USBSS IRQ_FRAME_THRESHOLD_RX0_2 Register (IRQFRAMETHOLDRX02)
1850
USBSS IRQ_FRAME_THRESHOLD_RX0_3 Register (IRQFRAMETHOLDRX03)
1850
USBSS IRQ_FRAME_THRESHOLD_RX0_2 Register (IRQFRAMETHOLDRX02) Field Descriptions
1850
USBSS IRQ_FRAME_THRESHOLD_RX0_3 Register (IRQFRAMETHOLDRX03) Field Descriptions
1850
USBSS IRQ_FRAME_THRESHOLD_TX1_0 Register (IRQFRAMETHOLD10)
1851
USBSS IRQ_FRAME_THRESHOLD_TX1_1 Register (IRQFRAMETHOLD11)
1851
USBSS IRQ_FRAME_THRESHOLD_TX1_0 Register (IRQFRAMETHOLD10) Field Descriptions
1851
USBSS IRQ_FRAME_THRESHOLD_TX1_1 Register (IRQFRAMETHOLDTX11) Field Descriptions
1851
USBSS IRQ_FRAME_THRESHOLD_TX1_2 Register (IRQFRAMETHOLD12)
1852
USBSS IRQ_FRAME_THRESHOLD_TX1_3 Register (IRQFRAMETHOLD13)
1852
USBSS IRQ_FRAME_THRESHOLD_TX1_2 Register (IRQFRAMETHOLDTX12) Field Descriptions
1852
USBSS IRQ_FRAME_THRESHOLD_TX1_3 Register (IRQFRAMETHOLDTX13) Field Descriptions
1852
USBSS IRQ_FRAME_THRESHOLD_RX1_0 Register (IRQFRAMETHOLDRX10)
1853
USBSS IRQ_FRAME_THRESHOLD_RX1_1 Register (IRQFRAMETHOLDRX11)
1853
USBSS IRQ_FRAME_THRESHOLD_RX1_0 Register (IRQFRAMETHOLDRX10) Field Descriptions
1853
USBSS IRQ_FRAME_THRESHOLD_RX1_1 Register (IRQFRAMETHOLDRX11) Field Descriptions
1853
USBSS IRQ_FRAME_THRESHOLD_RX1_2 Register (IRQFRAMETHOLDRX12)
1854
USBSS IRQ_FRAME_THRESHOLD_RX1_3 Register (IRQFRAMETHOLDRX13)
1854
USBSS IRQ_FRAME_THRESHOLD_RX1_2 Register (IRQFRAMETHOLDRX12) Field Descriptions
1854
USBSS IRQ_FRAME_THRESHOLD_RX1_3 Register (IRQFRAMETHOLDRX13) Field Descriptions
1854
USBSS IRQ_FRAME_ENABLE_0 Register (IRQFRAMEENABLE0)
1855
USBSS IRQ_FRAME_ENABLE_0 Register (IRQFRAMEENABLE0) Field Descriptions
1855
USBSS IRQ_FRAME_ENABLE_1 Register (IRQFRAMEENABLE1)
1856
USBSS IRQ_FRAME_ENABLE_1 Register (IRQFRAMEENABLE1) Field Descriptions
1856
USB0 Controller Registers
1857
USB0 Revision Register (USB0REV)
1858
USB0 Revision Register (USB0REV) Field Descriptions
1858
USB0 Control Register (USB0CTRL)
1859
USB0 Control Register (USB0CTRL) Field Descriptions
1859
USB0 Status Register (USB0STAT)
1860
USB0 IRQ_MERGED_STATUS Register (USB0IRQMSTAT)
1860
USB0 Status Register (USB0STAT) Field Descriptions
1860
USB0 IRQ_MERGED_STATUS Register (USB0IRQMSTAT) Field Descriptions
1860
USB0 IRQ_EOI Register (USB0IRQEOI)
1861
USB0 IRQ_EOI Register (USB0IRQEOI) Field Descriptions
1861
USB0 IRQ_STATUS_RAW_0 Register (USB0IRQSTATRAW0)
1862
USB0 IRQ_STATUS_RAW_0 Register (USB0IRQSTATRAW0) Field Descriptions
1862
USB0 IRQ_STATUS_RAW_1 Register (USB0IRQSTATRAW1)
1864
USB0 IRQ_STATUS_RAW_1 Register (USB0IRQSTATRAW1) Field Descriptions
1864
USB0 IRQ_STATUS_0 Register (USB0IRQSTAT0)
1865
USB0 IRQ_STATUS_0 Register (USB0IRQSTAT0) Field Descriptions
1865
USB0 IRQ_STATUS_1 Register (USB0IRQSTAT1)
1867
USB0 IRQ_STATUS_1 Register (USB0IRQSTAT1) Field Descriptions
1867
USB0 IRQ_ENABLE_SET_0 Register (USB0IRQENABLESET0)
1868
USB0 IRQ_ENABLE_SET_0 Register (USB0IRQENABLESET0) Field Descriptions
1868
USB0 IRQ_ENABLE_SET_1 Register (USB0IRQENABLESET1)
1870
USB0 IRQ_ENABLE_SET_1 Register (USB0IRQENABLESET1) Field Descriptions
1870
USB0 IRQ_ENABLE_CLR_0 Register (USB0IRQENABLECLR0)
1871
USB0 IRQ_ENABLE_CLR_0 Register (USB0IRQENABLECLR0) Field Descriptions
1871
USB0 IRQ_ENABLE_SET_1 Register (USB0IRQENABLECLR1)
1873
USB0 IRQ_ENABLE_CLR_1 Register (USB0IRQENABLECLR1) Field Descriptions
1873
USB0 Tx Mode Register (USB0TXMODE)
1874
USB0 Tx Mode Register (USB0TXMODE) Field Descriptions (USB0TXMODE) Field Descriptions
1874
USB0 Rx Mode Register (USB0RXMODE)
1876
USB0 Rx Mode Register (USB0RXMODE) Field Descriptions
1876
USB0 Generic RNDIS Epn Size Register (Usb0Genrndisepn)
1878
USB0 Generic RNDIS Epn Size Register (Usb0Genrndisepn) Field Descriptions
1878
USB0 Auto Req Register (USB0AUTOREQ)
1879
USB0 Auto Req Register (USB0AUTOREQ) Field Descriptions
1879
USB0 SRP Fix Time Register (USB0SRPFIXTIME)
1881
USB0 SRP Fix Time Register (USB0SRPFIXTIME) Field Descriptions
1881
USB0 Teardown Register (USB0TDOWN)
1882
USB0 Teardown Register (USB0TDOWN) Field Descriptions
1882
USB0 PHY UTMI Register (USB0UTMI)
1883
USB0 PHY UTMI Register (USB0UTMI) Field Descriptions
1883
USB0 MGC UTMI Loopback Register (USB0UTMILB)
1884
USB0 MGC UTMI Loopback Register (USB0UTMILB) Field Descriptions
1884
USB0 Mode Register (USB0MODE)
1885
USB0 Mode Register (USB0MODE) Field Descriptions
1885
USB1 Controller Registers
1886
USB1 Revision Register (USB1REV)
1887
USB1 Revision Register (USB1REV) Field Descriptions
1887
USB1 Control Register (USB1CTRL)
1888
USB1 Control Register (USB1CTRL) Field Descriptions
1888
USB1 Status Register (USB1STAT)
1889
USB1 IRQ_MERGED_STATUS Register (USB1IRQMSTAT)
1889
USB1 Status Register (USB1STAT) Field Descriptions
1889
USB1 IRQ_MERGED_STATUS Register (USB1IRQMSTAT) Field Descriptions
1889
USB1 IRQ_EOI Register (USB1IRQEOI)
1890
USB1 IRQ_EOI Register (USB1IRQEOI) Field Descriptions
1890
USB1 IRQ_STATUS_RAW_0 Register (USB1IRQSTATRAW1)
1891
USB1 IRQ_STATUS_RAW_0 Register (USB1IRQSTATRAW1) Field Descriptions
1891
USB1 IRQ_STATUS_RAW_1 Register (USB1IRQSTATRAW1)
1893
USB1 IRQ_STATUS_RAW_1 Register (USB1IRQSTATRAW1) Field Descriptions
1893
USB1 IRQ_STATUS_0 Register (USB1IRQSTAT0)
1895
USB1 IRQ_STATUS_0 Register (USBIRQSTAT0) Field Descriptions
1895
USB1 IRQ_STATUS_1 Register (USB0IRQSTAT1)
1897
USB1 IRQ_STATUS_1 Register (USB0IRQSTAT1) Field Descriptions
1897
USB1 IRQ_ENABLE_SET_0 Register (USB1IRQENABLESET0)
1899
USB1 IRQ_ENABLE_SET_0 Register (USB1IRQENABLESET0) Field Descriptions
1899
USB1 IRQ_ENABLE_SET_1 Register (USB1IRQENABLESET1)
1901
USB1 IRQ_ENABLE_SET_1 Register (USB1IRQENABLESET1) Field Descriptions
1901
USB1 IRQ_ENABLE_CLR_0 Register (USB1IRQENABLECLR0)
1903
USB1 IRQ_ENABLE_CLR_0 Register (USB1IRQENABLECLR0) Field Descriptions
1903
USB1 IRQ_ENABLE_CLR_1 Register (USB1IREENABLECLR1)
1905
USB1 IRQ_ENABLE_CLR_1 Register (USB1IREENABLECLR1) Field Descriptions
1905
USB1 Tx Mode Register (USB1TXMODE)
1907
USB1 Tx Mode Register (USB1TXMODE) Field Descriptions
1907
USB1 Rx Mode Register (USB1RXMODE)
1909
USB1 Rx Mode Register (USB1RXMODE) Field Descriptions
1909
USB1 Generic RNDIS EP N Size Register (Usb1Genrndisepn)
1911
USB1 Generic RNDIS EP N Size Register (Usb1Genrndisepn) Field Descriptions
1911
USB1 Auto Req Register (USB1AUTOREQ)
1912
USB1 Auto Req Register (USB1AUTOREQ) Field Descriptions
1912
USB1 SRP Fix Time Register (USB1SRPFIXTIME)
1914
USB1 SRP Fix Time Register (USB1SRPFIXTIME) Field Descriptions
1914
USB1 Teardown Register (USB1TDOWN)
1915
USB1 Teardown Register (USB1TDOWN) Field Descriptions
1915
USB1 PHY UTMI Register (USB1UTMI)
1916
USB1 PHY UTMI Register (USB1UTMI) Field Descriptions
1916
USB1 MGC UTMI Loopback Register (USB1UTMILB)
1917
USB1 MGC UTMI Loopback Register (USB1UTMILB) Field Descriptions
1917
USB1 Mode Register (USB1MODE)
1918
USB1 Mode Register (USB1MODE) Field Descriptions
1918
CPPI DMA Revision Register (DMAREVID)
1919
20.9.3 CPPI DMA Controller Registers
1919
CPPI DMA Revision Registe (DMAREVID) Field Descriptions
1919
CPPI DMA Teardown Free Descriptor Queue Control Register (TDFDQ)
1920
CPPI DMA Emulation Control Register (DMAEMU)
1920
CPPI DMA Teardown Free Descriptor Queue Control Register (TDFDQ) Field Descriptions
1920
CPPI DMA Emulation Control Register (DMAEMU) Field Descriptions
1920
Tx Channel N Global Configuration Register (Txgcrn)
1921
Tx Channel N Global Configuration Register (Txgcrn) Field Descriptions
1921
Rx Channel N Global Configuration Register (Rxgcrn)
1922
Rx Channel N Global Configuration Register (Rxgcrn) Field Descriptions
1922
Rx Channel N Host Packet Configuration Register a (Rxhpcran)
1923
Rx Channel N Host Packet Configuration Register a (Rxhpcran) Field Descriptions
1923
Rx Channel N Host Packet Configuration Register B (Rxhpcrbn)
1924
Rx Channel N Host Packet Configuration Register B (Rxhpcrbn) Field Descriptions
1924
CPPI DMA Scheduler Control Register (DMA_SCHED_CTRL)
1925
20.9.4 CPPI DMA Scheduler Registers
1925
CPPI DMA Scheduler Table Word N Register (Wordn)
1926
CPPI DMA Scheduler Table Word N Register (Wordn) Field Descriptions
1926
20.9.5 CPPI DMA Queue Manager Registers
1928
Queue Manager Revision Register (QMGRREVID)
1929
Queue Manager Queue Diversion Register (DIVERSION)
1929
Queue Manager Revision Register (QMGRREVID) Field Descriptions
1929
Queue Manager Queue Diversion Register (DIVERSION) Field Descriptions
1929
Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0)
1930
Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1)
1930
Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) Field Descriptions
1930
Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) Field Descriptions
1930
Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2)
1931
Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3)
1931
Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) Field Descriptions
1931
Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) Field Descriptions
1931
Queue Manager Free Descriptor/Buffer Starvation Count Register 4 (FDBSC4)
1932
Queue Manager Free Descriptor/Buffer Starvation Count Register 5 (FDBSC5)
1932
Queue Manager Free Descriptor/Buffer Starvation Count Register 4 (FDBSC4) Field Descriptions
1932
Queue Manager Free Descriptor/Buffer Starvation Count Register 5 (FDBSC5) Field Descriptions
1932
Queue Manager Free Descriptor/Buffer Starvation Count Register 6 (FDBSC6)
1933
Queue Manager Free Descriptor/Buffer Starvation Count Register 7 (FDBSC7)
1933
Queue Manager Free Descriptor/Buffer Starvation Count Register 6 (FDBSC6) Field Descriptions
1933
Queue Manager Free Descriptor/Buffer Starvation Count Register 7 (FDBSC7) Field Descriptions
1933
Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE)
1934
Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE)
1934
Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) Field Descriptions
1934
Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) Field Descriptions
1934
Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE)
1935
Queue Manager Queue Pending Register 0 (PEND0)
1935
Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) Field Descriptions
1935
Queue Manager Queue Pending Register 0 (PEND0) Field Descriptions
1935
Queue Manager Queue Pending Register 1 (PEND1)
1936
Queue Manager Queue Pending Register 2 (PEND2)
1936
Queue Manager Queue Pending Register 3 (PEND3)
1936
Queue Manager Queue Pending Register 1 (PEND1) Field Descriptions
1936
Queue Manager Queue Pending Register 2 (PEND1) Field Descriptions
1936
Queue Manager Queue Pending Register 3 (PEND3) Field Descriptions
1936
Queue Manager Queue Pending Register 4 (PEND4)
1937
Queue Manager Memory Region R Base Address Register (Qmemrbaser)
1937
Queue Manager Queue Pending Register 4 (PEND4) Field Descriptions
1937
Queue Manager Memory Region R Base Address Register (Qmemrbaser) Field Descriptions
1937
Queue Manager Memory Region R Control Register (Qmemrctrlr)
1938
Queue Manager Queue N Register a (Ctrlan)
1938
Queue Manager Memory Region R Control Register (Qmemrctrlr) Field Descriptions
1938
Queue Manager Queue N Register a (Ctrlan) Field Descriptions
1938
Queue Manager Queue N Register B (Ctrlbn)
1939
Queue Manager Queue N Register C (Ctrlcn)
1939
Queue Manager Queue N Register B (Ctrlbn) Field Descriptions
1939
Queue Manager Queue N Register C (Ctrlcn) Field Descriptions
1939
Queue Manager Queue N Register D (Ctrldn)
1940
Queue Manager Queue N Status Register a (Qstatan)
1940
Queue Manager Queue N Register D (Ctrldn) Field Descriptions
1940
Queue Manager Queue N Status Register a (Qstatan) Field Descriptions
1940
Queue Manager Queue N Status Register B (Qstatbn)
1941
Queue Manager Queue N Status Register C (Qstatcn)
1941
Queue Manager Queue N Status Register B (Qstatbn) Field Descriptions
1941
Queue Manager Queue N Status Register C (Qstatcn) Field Descriptions
1941
Common USB Registers
1942
Additional Control and Configuration Registers
1942
Function Address Register (Usbn_Faddr)
1943
Power Management Register (Usbn_Power)
1943
Interrupt Register for Receive Endpoints 1 to 15 (INTRRX)
1945
Interrupt Register for Receive Endpoints 1 to 15 (INTRRX) Field Descriptions
1945
Interrupt Enable Register for INTRTX (INTRTXE)
1946
Interrupt Enable Register for INTRTX (INTRTXE) Field Descriptions
1946
Interrupt Enable Register for INTRRX (INTRRXE)
1947
Interrupt Enable Register for INTRRX (INTRRXE) Field Descriptions
1947
Interrupt Register for Common USB Interrupts (Usbn_Intrusb)
1948
Interrupt Enable Register for INTRUSB (Usbn_Intrusbe)
1949
Frame Number Register (Usbn_Frame)
1949
Index Register for Selecting the Endpoint Status and Control Registers (Usbn_Index) Field
1950
Register to Enable the USB 2.0 Test Modes (Usbn_Testmode)
1951
Indexed Region Registers
1952
Count 0 Register (Usbn_Count0)
1961
Receive Count Register (Usbn_Rxcount)
1961
Type Register (Host Mode Only) (Usbn_Host_Type0)
1962
Transmit Type Register (Host Mode Only) (Usbn_Host_Txtype)
1963
Naklimit0 Register (Host Mode Only) (Usbn_Host_Naklimit0)
1964
Transmit Interval Register (Host Mode Only) (Usbn_Host_Txinterval)
1965
Receive Type Register (Host Mode Only) (Usbn_Host_Rxtype)
1966
Transmit Interval Register (Host Mode Only) (Usbn_Host_Rxinterval) Field Descriptions
1967
Configuration Data Register (Usbn_Configdata)
1968
Device Control Register (Usbn_Devctl)
1970
Transmit Endpoint FIFO Size Register (Usbn_Txfifosz)
1971
Receive Endpoint FIFO Size Register (Usbn_Rxfifosz)
1972
Transmit Endpoint FIFO Address Register (Usbn_Txfifoaddr)
1973
Receive Endpoint FIFO Address Register (Usbn_Rxfifoaddr)
1974
Hardware Version Register (Usbn_Hwvers)
1974
Target Endpoint Control Registers
1975
Transmit Function Address (Usbn_Txfuncaddrm) Field Descriptions
1975
Transmit Hub Address Register (Usbn_Txhubaddrm)
1976
Receive Function Address Register (Usbn_Rxfuncaddrm)
1977
Transmit Hub Port Register (Usbn_Txhubportm) Field Descriptions
1977
Receive Hub Address Register (Usbn_Rxhubaddrm)
1978
Receive Hub Port Register (Usbn_Rxhubportm)
1978
CM_DEFAULT_L3_SLOW_CLKSTCTRL Register
1980
CM_DEFAULT_L3_SLOW_CLKSTCTRL Register Field Descriptions
1980
USB_CTRL Register
1981
USB_CTRL Register Field Descriptions
1981
USBPHY_CTRL0 Register
1982
USBPHY_CTRL0 Register Field Descriptions
1982
USBPHY_CTRL1 Register
1983
USBPHY_CTRL0 Register Field Descriptions
1983
Acronyms and Abbreviations
1986
Naming Conventions
1987
Public ROM Code Architecture
1988
Public ROM Code Boot Procedure
1989
ROM Memory Map
1990
ROM Exception Vectors
1990
Dead Loops
1991
Public RAM Memory Map
1992
RAM Exception Vectors
1992
Tracing Data
1993
ROM Code Start-Up Sequence
1994
ROM Code Default Clock Settings
1995
MBOOT Configuration Pins
1997
Fast External Boot
1999
Memory Booting
2000
GPMC XIP Timings
2001
XIP Timings Parameters
2002
Pins Used for nor Boot
2002
Image Shadowing on GP Device
2003
GPMC NAND Timings
2004
NAND Timings Parameters
2005
ONFI Parameters
2005
Supported NAND Devices
2005
4Th NAND ID Data Byte
2006
Pins Used for NANDI2C Boot for I2C EEPROM Access
2007
NAND Geometry Information on I2C EEPROM
2007
NAND Device Detection
2008
NAND Invalid Blocks Detection
2009
NAND Read Sector Procedure
2010
Pins Used for NAND Boot
2010
Contents SPRUGX9 - 15 April
2011
List of Figures SPRUGX9 - 15 April
2011
SPRUGX9 - 15 April 2011
2011
ECC Data Mapping for 2KB Page and 8B BCH Encoding
2011
ECC Data Mapping for 4KB Page and 16B BCH Encoding
2012
SD Booting
2013
SD Detection Procedure
2014
SD Booting, Get Booting File
2016
Master Boot Record Structure
2017
Partition Entry
2017
Partition Types
2017
MBR Detection Procedure
2018
MBR, Get Partition
2019
FAT Boot Sector
2020
Peripheral Booting Procedure
2021
Pins Used for Ethernet Boot
2022
Pcie Peripheral Booting Procedure
2023
Pcie 32 BAR Window Size Configuration
2023
Pcie 64 BAR Window Size Configuration
2024
Pcie BAR Window Base Address and Offset Configuration
2024
Pins Used for UART Boot
2025
ASIC ID Structure
2025
ID Sub Block
2025
Secure Model Sub Block
2026
Public ID Sub Block
2026
Root Key Hash Sub Block
2026
Checksum Sub Block
2026
Image Formats
2027
TOC Structure
2028
GP Device Image Format
2028
TOC Item Fields
2029
Filenames in TOC
2029
Booting Parameters Structure
2030
Tracing Vectors
2031
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