Table of Contents
Advertisement
www.ti.com
Table 7-29. System Test Register (I2C_SYSTEST) Field Descriptions (continued)
Bit
Field
13-12
TMODE
11
SSB
10-9
Reserved
8
SCL_I_FUNC
7
SCL_O_FUNC
6
SDA_I_FUNC
5
SDA_O_FUNC
4
Reserved
3
SCL_I
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Preliminary
Value
Description
Test mode select. In normal functional mode (ST_EN = 0), these bits are don't care. They are
always read as 00 and a write is ignored.
In system test mode (ST_EN = 1), these bits can be set according to the following table to
permit various system tests.
0
Functional mode (default)
1h
Reserved
2h
Test of SCL counters (SCLL, SCLH, PSC). SCL provides a permanent clock with master
mode.
3h
Loop back mode select + SDA/SCL IO mode select
Values after reset are low (2 bits).
SCL counter test mode: in this mode, the SCL pin is driven with a permanent clock as if
mastered with the parameters set in the I2C_PSC, I2C_SCLL, and I2C_SCLH registers.
Loop back mode: in the master transmit mode only, data transmitted out of the I2C_DATA
register (write action) is received in the same I2C_DATA register via an internal path through
the FIFO buffer. The DMA and interrupt requests are normally generated if enabled.
SDA/SCL IO mode: in this mode, the SCL IO and SDA IO are controlled via the
I2C_SYSTEST [5:0] register bits.
Set status bits. Writing 1 into this bit also sets the 6 read/clear-only status bits contained in
I2C_IRQSTATUS_RAW register (bits 5:0) to 1. Writing 0 into this bit doesn't clear status bits
that are already set; only writing 1 into a set status bit can clear it (see
I2C_IRQSTATUS_RAW operation). This bit must be cleared prior attempting to clear a status
bit.
0
No action
1
Set all interrupt status bits to 1
Value after reset is low.
0
Reserved
SCL line input value (functional mode). This read-only bit returns the logical state taken by the
SCL line (either 1 or 0). It is active both in functional and test mode
Read:0
Read 0 from SCL line
Read:1
Read 1 from SCL line
Value after reset is low.
SCL line output value (functional mode). This read-only bit returns the value driven by the
module on the SCL line (either 1 or 0). It is active both in functional and test mode.
Read:0
Driven 0 on SCL line
Read:1
Driven 1 on SCL line
Value after reset is low.
SDA line input value (functional mode). This read-only bit returns the logical state taken by the
SDA line (either 1 or 0). It is active both in functional and test mode.
Read:0
Read 0 from SDA line
Read:1
Read 1 from SDA line
Value after reset is low.
SDA line output value (functional mode). This read-only bit returns the value driven by the
module on the SDA line (either 1 or 0). It is active both in functional and test mode.
Read:0
Driven 0 to SDA line
Read:1
Driven 1 to SDA line
Value after reset is low.
0
Reserved
SCL line sense input value. In normal functional mode (ST_EN = 0), this read-only bit always
reads 0. In system test mode (ST_EN = 1 & TMODE = 11), this read-only bit returns the
logical state taken by the SCL line (either 1 or 0).
Read:0
Read 0 from SCL line
Read:1
Read 1 from SCL line
Value after reset is low.
© 2011, Texas Instruments Incorporated
Inter-Integrated Circuit (I2C) Controller Module
Registers
893
Advertisement
Table of Contents
