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Registers
Table 9-32. Interrupt Status Register (SD_STAT) Field Descriptions (continued)
Bit
Field
2
BGE
1
TC
0
CC
994
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Preliminary
Value
Description
Block gap event. When a stop at block gap is requested (SD_HCTL[16] SBGR bit), this bit is
automatically set when transaction is stopped at the block gap during a read or write
operation.
This event does not occur when the stop at block gap is requested on the last block.
In read mode, a 1-to-0 transition of the SD_DAT line active status (SD_PSTATE[2] DLA bit)
between data blocks generates a Block gap event interrupt.
Read 0
No block gap event
Write 0
Status bit unchanged
Read 1
Transaction stopped at block gap
Write 1
Status is cleared
Transfer completed. This bit is always set when a read/write transfer is completed or between
two blocks when the transfer is stopped due to a stop at block gap request (SD_HCTL[16]
SBGR bit).
This bit is also set when exiting a command in a busy state (if the command has a busy
notification capability).
In Read modeThis bit is automatically set on completion of a read transfer (SD_PSTATE[9]
RTA bit).
In write modeThis bit is set automatically on completion of the SD_DAT line use
(SD_PSTATE[2] DLA bit).
Read 0
No transfer complete
Write 0
Status bit unchanged
Read 1
Data transfer complete
Write 1
Status is cleared
Command complete. This bit is set when a 1-to-0 transition occurs in the register command
inhibit (SD_PSTATE[0] CMDI bit)
If the command is a type for which no response is expected, then the command complete
interrupt is generated at the end of the command. A command timeout error (SD_STAT[16]
CTO bit) has higher priority than command complete (SD_STAT[0] CC bit).
If a response is expected but none is received, then a command timeout error is detected and
signaled instead of the command complete interrupt.
Read 0
No command complete
Write 0
Status bit unchanged
Read 1
Command complete
Write 1
Status is cleared
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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