Dev_Cap2 Register; Dev_Stat_Ctrl2 Register; Dev_Cap2 Register Field Descriptions; Dev_Stat_Ctrl2 Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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13.4.8.10 DEV_CAP2 Register

31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-5 Reserved
4 CMPL_TO_DIS_SUPP
3-0 CMPL_TO_EN

13.4.8.11 DEV_STAT_CTRL2 Register

31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-5 Reserved
4 CMPL_TO_DIS
3-0 CMPL_TO
SPRUGX9 – 15 April 2011
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Preliminary
Figure 13-114. DEV_CAP2 Register
Reserved
R-0
Table 13-121. DEV_CAP2 Register Field Descriptions
Value Description
0 Reserved
0 Completion timeout disable supported
0-Fh Completion timeout ranges supported. Applicable to RC/EP.
Figure 13-115. DEV_STAT_CTRL2 Register
Reserved
R-0
Table 13-122. DEV_STAT_CTRL2 Register Field Descriptions
Value Description
0 Reserved
0 Completion timeout disabled
0-Fh Completion timeout value
© 2011, Texas Instruments Incorporated
Reserved
R-0
5 4
CMPL_TO_DIS_SUPP
R-1
Reserved
R-0
5 4
CMPL_TO_DIS
R/W-0
Peripheral Component Interconnect Express (PCIe)
Registers
16
3 0
CMPL_TO_EN
R-Fh
5
3 0
CMPL_TO
R/W-0
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