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NOTE: All other configuration registers need to be at the reset value.
The UART mode interrupts are used for the SIR Free Format mode but many of them are
not relevant (XOFF, RTS, CTS, Modem status register, .......).
19.2.4.1.9 Programming Models
Example 19-1. Receive IrDA
Receive IrDA frame with parity forced to 1, baud-rate = 112.5Kbs, FIFOs disabled.
•
MDR1 = 01h
– MDR1[2:0] = 001b: SIR mode
•
LCR = A8h
– LCR[7] = 1: access to write DLL and DLH
– LCR[5:3] = 101: set parity type to forced 1 (default: no parity).
– optional: LCR[2] = 1: set number of stop bits to 2 (default: 1)
– optional: LCR[1:0] = 11b: set word length to 8 bits (default: 5)
•
DLL = 1Ah: 115.2 Kbs
•
DLH = 0h: 115.2 Kbs
•
LCR = 28h: LCR[7] = 0 disables access to DLL and DLH and gives access to MCR, FCR, IER, BLR,
EBLR, RHR
•
optional: IER = 1: enable RHR interrupt
Example 19-2. Transmit IrDA
Transmit IrDA 6bytes frame with no parity, baud-rate = 112.5Kbs, FIFOs disabled, 3/16 encoding.
•
MDR1 = 41h
– MDR1[2:0] = 001b: SIR mode
– MDR1[6] = 1: SIP is generated automatic after each transmission
•
LCR = BFh: gives you access to EFR
•
EFR = 10h: enhanced functions write enable
•
LCR = 86h
– LCR[7] = 1: access to write DLL and DLH
– LCR[2] = 1: set number of stop bits to 2 (default: 1)
– LCR[1:0] = 10b: set word length to 7 bits (default: 5)
•
DLL = 1Ah: 115.2 Kbs
•
DLH = 0h: 115.2 Kbs
•
LCR = 06h: LCR[7] = 0 disables access to DLL and DLH and gives access to MCR, FCR, IER, BLR,
EBLR, THR
•
MCR =01h: force DTR output to active (low)
•
optional: IER = 02h: enable THR interrupt
•
TXFLL = 06h: transmit frame length is 6 bytes
•
EBLR = 08: transmit 7 starts of frame
•
optional: set ACREG[7] = 1: selects SIR pulse width to be 1.6 µs (default 3/16 bit period).
•
THR = desired data to be transmitted
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Architecture
1691
UART/IrDA/CIR Module
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